Abstract: A memory manager includes an internal memory including a V2H (virtual address to hash function) table in which at least one virtual address group and a type information on a hash function mapped to the virtual address group are stored, and an exception mapping table in which at least one exception virtual address not translated into a physical address by the hash function in the virtual address group and a physical address mapped to the exception virtual address are stored; and a hash function module configured to check, when a virtual address is provided from a host, type information on a hash function mapped to a virtual address group including the virtual address, by referring to the V2H table included in the internal memory, and translate the virtual address into a physical address by using the hash function corresponding to the type information.

Abstract: Disclosed herein is a method of manufacturing an electrode for a secondary battery, including: a process of continuously forming two or more slurry coated parts on one surface or both surfaces of metal foil in a second direction which is a longitudinal direction of the metal foil so that a non-coated part which an electrode slurry is not coated is positioned between the slurry coated parts coated with the electrode slurry including an electrode active material in a first direction which is a transverse direction of the metal foil; a process of forming mixture coated parts by drying the slurry coated parts and rolling by a roller; and a process of forming electrode strips by slitting the non-coated part in the second direction, wherein before continuously forming the slurry coated parts, while continuously forming the slurry coated parts, or between continuously forming the slurry coated parts and forming the mixture coated parts, the method further includes a process of forming non-continuous linear slits in

Abstract: Provided is a battery module that is simple, compact and sure to improve the mechanical performance against cell pressing, swelling and impacts and a method for fabricating the same. The battery module according to the present disclosure includes two or more pouch-type battery cells, and a hollow quadrilateral monoframe in which the battery cells are received, wherein the monoframe has a first opening and a second opening that are open to two sides in lengthwise direction of the battery cells, wherein a cushion bag is provided in close contact between the battery cells and the monoframe.

Abstract: Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.

Abstract: Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.

Abstract: The present disclosure provides a device for cleaning a protective film to be attached to an outer surface of a laminate during a lamination process of heating and pressing the laminate of electrodes and a separator to produce an electrode assembly of a battery cell, including a feed roll configured to supply the protective film, at least one guide roll configured to guide a progress of the protective film supplied from the feed roll, a cleaning roll located between the feed roll and a winding roll and configured to remove foreign substances remaining on the protective film supplied from the feed roll, and the winding roll configured to wind the protective film from which foreign substances have been removed by the cleaning roll, wherein a nano thin film is formed on an outer surface of the cleaning roll to adsorb and remove the foreign substances remaining on the protective film.

Abstract: Disclosed is a battery pack, which may effectively prevent a bending phenomenon caused by a load while ensuring excellent assembling and compatibility and light weight, and a vehicle including the battery pack. The battery pack includes: a plurality of battery modules including at least one secondary battery accommodated in a module case and a side surface coupling unit provided at an outer side portion of the module case, the plurality of battery modules being arranged in a lateral direction so that side surfaces thereof face each other with intervals therebetween; and a fixing member having an interposing portion interposed between side surfaces of two adjacent battery modules and coupled to the side surface coupling units of the two adjacent battery modules so that two or more battery modules are coupled and fixed.

Abstract: An electronic device and a control method therefor are provided. The electronic device comprises: a housing including a roll; a touch display which is wound on a roll, is capable of changing the size of a display area according to the rotation of the roll, and detects a touch of a user; a sensing part for sensing the size of the display area; and a processor which is electrically connected to the display and the sensing part, wherein if the size of the display area increases by the rotation of the roll while a user touch is detected in one area of the touch display while an execution screen of an application is being provided in the display area, the processor may control the touch display so as to provide new information to the display area.

Abstract: Provided is a battery module that is simple, compact and sure to improve the mechanical performance against cell pressing, swelling and impacts and a method for fabricating the same. The battery module according to the present disclosure includes two or more pouch-type battery cells, and a hollow quadrilateral monoframe in which the battery cells are received, wherein the monoframe has a first opening and a second opening that are open to two sides in lengthwise direction of the battery cells, wherein a cushion bag is provided in close contact between the battery cells and the monoframe.

Abstract: Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.

Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.

Abstract: Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.

Abstract: A photovoltaic cell structure for converting light energy into electrical energy is provided herein. One of skill will appreciate having, for example, a photovoltaic cell structure configured to increase capture of electron hole pairs. Such a photovoltaic cell structure can include a semiconductor substrate configured with a circuit having a P-N junction: and, a P/P+ junction; wherein, the P-N junction and the P/P+ junction are separated by a maximum distance of no more than 3.5 microns to increase the capture of electron hole pairs by decreasing the distance the holes have to travel for the capture.

Abstract: The present structure and method for fabrication thereof provides a photovoltaic cell structure for converting light energy into electrical energy. According to one embodiment, a pillared photovoltaic cell structure comprises an array of pillars that are situated closely to each other to take advantage of both the wave-like properties and the particle-like properties of light to enhance the energy conversion efficiency of the photovoltaic cell. According to one embodiment, a pillared photovoltaic cell structure incorporating self-aligned P/P+ junctions enable holes generated near the top surface of the cell structure to be captured by the self-aligned P/P+ junctions.

Abstract: The present structure and method for fabrication thereof provides a photovoltaic cell structure for converting light energy into electrical energy. According to one embodiment, a pillared photovoltaic cell structure comprises an array of pillars that are situated closely to each other to take advantage of both the wave-like properties and the particle-like properties of light to enhance the energy conversion efficiency of the photovoltaic cell. According to one embodiment, a pillared photovoltaic cell structure incorporating self-aligned P/P+ junctions enable holes generated near the top surface of the cell structure to be captured by the self-aligned P/P+ junctions.

Abstract: A method of forming a non-volatile DRAM includes, in part: forming p-well and an n-well between two trench isolation regions formed in a semiconductor substrate, forming a polysilicon control gate of the non-volatile device disposed in the non-volatile DRAM, forming a first oxide spacer above portions of the body region and adjacent said first control gate, forming gate oxide layers of varying thicknesses above the body region, forming the guiding gate of the non-volatile device and the gate of an associated passgate transistor, forming LDD implant regions of the non-volatile device and the associated pass-gate transistor, forming source/drain regions of the non-volatile device and the associated pass-gate transistor, depositing a dielectric layer over the polysilicon guiding gate of the non-volatile device and the polysilicon gate of the associated passgate transistor, forming polysilicon landing pads, and forming polysilicon vertical walls defining capacitor plates of the non-volatile DRAM capacitor.

Abstract: A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon layer above the second oxide layer, forming lightly doped areas in the body region; forming a second spacer above the body region, forming source and drain regions of the non-volatile device and the MOS transistor of the non-volatile DRAM; forming a third polysilicon layer over portions of the lightly doped areas to form polysilicon landing pads; forming a third dielectric layer above the polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.

Abstract: A method of forming a self-aligned non-volatile device, includes, in part: forming trench isolation regions, forming a well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric, a first polysilicon gate, and a second dielectric layer, respectively, above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, removing the second polysilicon layer and the layers below it that are exposed in a via formed using a mask, thereby forming self-aligned source/drain regions.

Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SRAM cell and a second non-volatile device is disposed therein. If so adapted, the SRAM cells and/or the non-volatile devices when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the SRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the SRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.

Abstract: A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. The device includes a source terminal, a drain terminal, a guiding gate terminal, a control gate terminal, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.