Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The non-volatile device is erased prior to being programmed. Programming of the non-volatile device may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM is loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile device is restored in the DRAM cell.

Abstract: In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.

Abstract: A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. The device includes a source terminal, a drain terminal, a guiding gate terminal, a control gate terminal, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.

Abstract: In accordance with the present invention, a memory cell includes both non-volatile and SRAM cells. The non-volatile memory cell includes two MNOS transistors forming a differential pair. The SRAM cell includes a pair of MOS select transistors and a pair of cross-coupled MOS transistors. The MOS select transistors are adapted to couple the true and complement bitlines associated with the memory cell to various terminals of the cross-coupled MOS transistors, thereby to load data into the SRAM. During power-off, data is loaded from the SRAM into the non-volatile memory cell. During a subsequent read of the non-volatile memory cell, the SRAM is reloaded with data it had prior to the power-off. Because the MNOS transistors of the non-volatile memory cell operate differentially, data read errors caused by over-erase are reduced. Because the voltages applied during programming and erase cycle of the non-volatile memory cell are relatively small, the memory cell consumes relatively small amount of power.

Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SRAM cell and a second non-volatile device is disposed therein If so adapted, the SRAM cells and/or the non-volatile devices when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the SRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the SRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.

Abstract: A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000A and small spaces down to 700 Å. The DRAM has active isolations, word lines, cup-shaped vertical capacitor walls, and bit lines. The process for forming small dimensions having this narrow width, narrow wall and the small space in ranges down 800 Å comprises depositing a form material on the surface of a product material. A portion of the form material is removed by RIE etching by using the lithography technique. A layer of masking material is deposited over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material. Masking material is removed by vertical RIE until the form material is exposed, leaving a predetermined width of masking material.

Abstract: A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000 .ANG. and small spaces down to 700 .ANG.. The DRAM has active isolations, word lines, cup-shaped vertical capacitor walls, and bit lines. The process for forming small dimensions having this narrow width, narrow wall and the small space in ranges down 800 .ANG. comprises depositing a form material on the surface of a product material. A portion of the form material is removed by RIE etching by using the lithography technique. A layer of masking material is deposited over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material. Masking material is removed by vertical RIE until the form material is exposed, leaving a predetermined width of masking material.

Abstract: A semiconductor a semiconductor memory device including a plurality of normal blocks containing only normal memory cells without a redundant memory cell and a redundant block containing only redundant memory cells.

Abstract: There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.

Abstract: There is disclosed a stacked capacitor comprising a fin-shaped storage electrode of multiple polysilicon layers with supporting layers therebetween so as to compensate for the structural weakness of the fin-shaped storage electrode.

Abstract: There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.

Abstract: A method being capable of achieving the reduction in contact resistance between each layer when bringing a silicide layer into contact with a polycrystalline-silicon (polysilicon) layer in the manufacture of semiconductor devices. The method comprises the steps of forming a polysilicon layer and a silicide layer thereon over a partial top surface of a semiconductor substrate, forming an insulating layer over said silicide layer and the entire top surface of the substrate, forming a contact window by etching the partial area of the insulating layer over said silicide layer, and forming a polysilicon layer over the entire top surface of the substrate after performing ion-implantation through said contact window, wherein said ion-implantation is performed with N-type high doping into the silicide.

Abstract: SRAM device having a power supply voltage control circuit capable of preventing the failure of memory cells used for a long period of time, without lowering a power supply voltage is disclosed. The SRAM device includes a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells each coupled between a word line and each pair of bit lines, and a power supply regulating stage coupled to each memory cell, for decreasing a supply voltage delivered to each memory cell when an external power supply voltage exceeds a specified voltage level, and delivering the external power supply voltage to each memory cell when the external power supply voltage does not exceed the specified voltage level. If an external power supply voltage is lower than a voltage level Vc, the supply voltage is supplied as a power source of the memory cell.

Abstract: A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.