Patents by Inventor Kyu Hyun Choi
Kyu Hyun Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180374452Abstract: An electronic device and a control method therefor are provided. The electronic device comprises: a housing including a roll; a touch display which is wound on a roll, is capable of changing the size of a display area according to the rotation of the roll, and detects a touch of a user; a sensing part for sensing the size of the display area; and a processor which is electrically connected to the display and the sensing part, wherein if the size of the display area increases by the rotation of the roll while a user touch is detected in one area of the touch display while an execution screen of an application is being provided in the display area, the processor may control the touch display so as to provide new information to the display area.Type: ApplicationFiled: November 16, 2016Publication date: December 27, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-hyun CHOI, Hee-seok JEONG
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Publication number: 20180062127Abstract: Provided is a battery module that is simple, compact and sure to improve the mechanical performance against cell pressing, swelling and impacts and a method for fabricating the same. The battery module according to the present disclosure includes two or more pouch-type battery cells, and a hollow quadrilateral monoframe in which the battery cells are received, wherein the monoframe has a first opening and a second opening that are open to two sides in lengthwise direction of the battery cells, wherein a cushion bag is provided in close contact between the battery cells and the monoframe.Type: ApplicationFiled: August 31, 2017Publication date: March 1, 2018Applicant: LG CHEM, LTD.Inventors: Su-Hang LEE, Kyu-Hyun CHOI, Yong-Seok CHOI, Jin-Hak KONG
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Publication number: 20180047459Abstract: Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.Type: ApplicationFiled: April 13, 2017Publication date: February 15, 2018Applicant: Korea University Research and Business FoundationInventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi, Young Sun Han
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Publication number: 20180011770Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.Type: ApplicationFiled: July 5, 2017Publication date: January 11, 2018Applicant: Korea University Research and Business FoundationInventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi
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Publication number: 20170371753Abstract: Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.Type: ApplicationFiled: January 30, 2017Publication date: December 28, 2017Applicant: Korea University Research and Business FoundationInventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi
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Publication number: 20170229597Abstract: A photovoltaic cell structure for converting light energy into electrical energy is provided herein. One of skill will appreciate having, for example, a photovoltaic cell structure configured to increase capture of electron hole pairs. Such a photovoltaic cell structure can include a semiconductor substrate configured with a circuit having a P-N junction: and, a P/P+ junction; wherein, the P-N junction and the P/P+ junction are separated by a maximum distance of no more than 3.5 microns to increase the capture of electron hole pairs by decreasing the distance the holes have to travel for the capture.Type: ApplicationFiled: April 27, 2017Publication date: August 10, 2017Inventor: KYU HYUN CHOI
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Publication number: 20140329352Abstract: The present structure and method for fabrication thereof provides a photovoltaic cell structure for converting light energy into electrical energy. According to one embodiment, a pillared photovoltaic cell structure comprises an array of pillars that are situated closely to each other to take advantage of both the wave-like properties and the particle-like properties of light to enhance the energy conversion efficiency of the photovoltaic cell. According to one embodiment, a pillared photovoltaic cell structure incorporating self-aligned P/P+ junctions enable holes generated near the top surface of the cell structure to be captured by the self-aligned P/P+ junctions.Type: ApplicationFiled: July 16, 2014Publication date: November 6, 2014Inventor: Kyu Hyun Choi
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Publication number: 20100200065Abstract: The present structure and method for fabrication thereof provides a photovoltaic cell structure for converting light energy into electrical energy. According to one embodiment, a pillared photovoltaic cell structure comprises an array of pillars that are situated closely to each other to take advantage of both the wave-like properties and the particle-like properties of light to enhance the energy conversion efficiency of the photovoltaic cell. According to one embodiment, a pillared photovoltaic cell structure incorporating self-aligned P/P+ junctions enable holes generated near the top surface of the cell structure to be captured by the self-aligned P/P+ junctions.Type: ApplicationFiled: February 12, 2010Publication date: August 12, 2010Inventor: Kyu Hyun Choi
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Patent number: 7232717Abstract: A method of forming a non-volatile DRAM includes, in part: forming p-well and an n-well between two trench isolation regions formed in a semiconductor substrate, forming a polysilicon control gate of the non-volatile device disposed in the non-volatile DRAM, forming a first oxide spacer above portions of the body region and adjacent said first control gate, forming gate oxide layers of varying thicknesses above the body region, forming the guiding gate of the non-volatile device and the gate of an associated passgate transistor, forming LDD implant regions of the non-volatile device and the associated pass-gate transistor, forming source/drain regions of the non-volatile device and the associated pass-gate transistor, depositing a dielectric layer over the polysilicon guiding gate of the non-volatile device and the polysilicon gate of the associated passgate transistor, forming polysilicon landing pads, and forming polysilicon vertical walls defining capacitor plates of the non-volatile DRAM capacitor.Type: GrantFiled: May 28, 2003Date of Patent: June 19, 2007Assignee: O2IC, Inc.Inventors: Kyu Hyun Choi, Sheau-suey Li
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Patent number: 7186612Abstract: A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon layer above the second oxide layer, forming lightly doped areas in the body region; forming a second spacer above the body region, forming source and drain regions of the non-volatile device and the MOS transistor of the non-volatile DRAM; forming a third polysilicon layer over portions of the lightly doped areas to form polysilicon landing pads; forming a third dielectric layer above the polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.Type: GrantFiled: April 6, 2004Date of Patent: March 6, 2007Assignee: O2IC, Inc.Inventor: Kyu Hyun Choi
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Patent number: 6972229Abstract: A method of forming a self-aligned non-volatile device, includes, in part: forming trench isolation regions, forming a well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric, a first polysilicon gate, and a second dielectric layer, respectively, above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, removing the second polysilicon layer and the layers below it that are exposed in a via formed using a mask, thereby forming self-aligned source/drain regions.Type: GrantFiled: December 23, 2003Date of Patent: December 6, 2005Assignee: 02IC, Inc.Inventor: Kyu Hyun Choi
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Patent number: 6965524Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SRAM cell and a second non-volatile device is disposed therein. If so adapted, the SRAM cells and/or the non-volatile devices when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the SRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the SRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.Type: GrantFiled: March 19, 2003Date of Patent: November 15, 2005Assignee: O2IC, Inc.Inventor: Kyu Hyun Choi
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Patent number: 6965145Abstract: A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. The device includes a source terminal, a drain terminal, a guiding gate terminal, a control gate terminal, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.Type: GrantFiled: March 19, 2003Date of Patent: November 15, 2005Assignee: O2IC, Inc.Inventor: Kyu Hyun Choi
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Publication number: 20050231473Abstract: An apparatus and method for providing a bring-up simulation game in a mobile terminal that makes a call over a mobile communication network are provided. In the apparatus, a call detector monitors an incoming or outgoing call and collects bring-up call information from the monitored call. A call decider analyzes bring-up call information associated with a phone number mapped to a predetermined character among the collected bring-up call information, numerically quantizes the analyzed bring-up call information, and determines the growth stage of the character according to the numerical bring-up call information. A character controller updates the appearance and state of the character according to the growth stage of the character. A display displays the updated appearance and state of the character.Type: ApplicationFiled: April 6, 2005Publication date: October 20, 2005Inventors: Hun-Kee Kim, Kyu-Hyun Choi, Joo-Kwang Kim, Joo-Sang Ryu, Kyo-Sook Shin
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Patent number: 6954377Abstract: In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.Type: GrantFiled: March 19, 2003Date of Patent: October 11, 2005Assignee: O2IC, Inc.Inventors: Kyu Hyun Choi, Sheau-suey Li
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Publication number: 20050220044Abstract: An apparatus and method for performing a bring-up simulation to bring up a character are provided. In the apparatus, a sensor measures at least one of an ambient temperature of the mobile terminal, a remaining battery power of the mobile terminal and an amount of vibrations of the mobile terminal, a controller compares the measured value received from the sensor with a predetermined threshold, calculates bonus points and penalty points according to the measured value, and controls the state of a character according to the calculated bonus and penalty points, character generator sets or updates the state of the character according to internal conditions of the mobile terminal, external conditions of the mobile terminal and user interaction with the character via the mobile terminal corresponding to a control signal received from the controller, and a display for displaying the character in accordance with the state and growth stage of the character.Type: ApplicationFiled: March 30, 2005Publication date: October 6, 2005Inventors: Kyu-Hyun Choi, Joon-Sang Ryu, Kyo-Sook Shin, Hun-Kee Kim, Joo-Kwang Kim
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Publication number: 20050161718Abstract: A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon layer above the second oxide layer, forming lightly doped areas in the body region; forming a second spacer above the body region, forming source and drain regions of the non-volatile device and the MOS transistor of the non-volatile DRAM; forming a third polysilicon layer over portions of the lightly doped areas to form polysilicon landing pads; forming a third dielectric layer above the polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.Type: ApplicationFiled: April 6, 2004Publication date: July 28, 2005Applicant: O2IC, Inc.Inventor: Kyu Hyun Choi
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Publication number: 20050136592Abstract: A method of forming a self-aligned non-volatile device, includes, in part: forming trench isolation regions, forming a well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric, a first polysilicon gate, and a second dielectric layer, respectively, above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, removing the second polysilicon layer and the layers below it that are exposed in a via formed using a mask, thereby forming self-aligned source/drain regions.Type: ApplicationFiled: December 23, 2003Publication date: June 23, 2005Applicant: 02IC, Inc.Inventor: Kyu Hyun Choi
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Patent number: 6806148Abstract: A method of forming an integrated circuit, includes, in part: forming trench isolation in a semiconductor substrate, forming a first well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric layer above the first oxide layer, forming a first polysilicon gate layer above the first dielectric layer, forming a second dielectric layer above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, and forming a second spacer to define source and drain regions.Type: GrantFiled: May 28, 2003Date of Patent: October 19, 2004Assignee: O2IC, Inc.Inventors: Kyu Hyun Choi, Sheau-suey Li
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Patent number: 6798008Abstract: In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The non-volatile device is erased prior to being programmed. Programming of the non-volatile device may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM is loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile device is restored in the DRAM cell.Type: GrantFiled: March 19, 2003Date of Patent: September 28, 2004Assignee: 02IC, Inc.Inventor: Kyu Hyun Choi