Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: Disclosed is an image processing method. The method includes the steps of receiving an image obtained from a plurality of vehicles positioned on a road, storing the received images according to acquisition information of the received images; determining a reference image and a target image based on images having the same acquisition information among the stored images, performing an image registration using a plurality of feature points extracted from each of the determined reference image and target image, performing a transparency process for each of the reference image and the target image performed with the image registration, extracting static objects from the transparency-processed image, and comparing the extracted static objects with objects on an electronic map pre-stored to updating the electronic map data, when the objects on the electronic map data pre-stored are different from the extracted static objects.

Abstract: A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

Abstract: An apparatus and method for performing optical alignment between optical waveguide elements in manufacturing a surface mountable optical module, in which a plurality of optical waveguide elements are mounted on a surface of a mounting substrate, is disclosed. A controller performs recognition of the interference pattern included in the image information received from the camera, observes parallelism between the substrate support and the mounting substrate and between the mounting substrate and the optical waveguide element using the recognized pattern, generates a control signal to control the transport device according to the observed parallelism, and transmits the control signal to the transport device to perform control of the optical waveguide element.

Abstract: An apparatus for preventing a sub-frame of an electric vehicle with a wireless charging pad from being pushed back includes: a push bracket member having one side portion coupled to a front end module provided in front of a sub-frame of the electric vehicle and extending to be disposed between the sub-frame and a wireless charging pad mounted below the sub-frame. Upon a forward vehicle collision, the apparatus can induce deformation of the sub-frame equipped with the wireless charging pad to prevent the sub-frame from being pushed backward.

Abstract: A method in which a high-quality packet telephony terminal apparatus performing low-latency and lossless packet communication with a counterpart packet telephony terminal apparatus operates in an integrated network structure in which a time sensitive network (TSN) and a packet communication network are combined may be disclosed. The packet telephony terminal apparatus may perform packet telephony call processing, perform a TSN stream reservation procedure when the counterpart packet telephony terminal apparatus is capable of performing a TSN function for lossless packet communication, adjust a size of a dejitter buffer when the TSN stream reservation procedure is successful, and perform low-latency packet telephony communication through the minimized size of the dejitter buffer.

Abstract: A glass stress test method includes breaking a glass, analyzing a shape of a crack of a broken portion of the glass in a plan view, finding a breakage origin of the glass based on the shape of the crack in the plan view, analyzing a cross-section of the breakage origin, and calculating a stress of the glass based on a cross-sectional analysis result of the breakage origin. The stress of the glass is calculated as a value proportional to a floor constant defined by a condition of a floor surface disposed when the glass is broken.

Abstract: A semiconductor module includes a substrate; a plurality of semiconductor packages provided on the substrate; and an environment information indicator configured to display information related to an environment surrounding the plurality of semiconductor packages.

Abstract: In some embodiments, a memory system includes a memory device and a host configured to transmit, to the memory device, a command and address (C/A) signal and a clock signal, and to transmit or receive data signals to or from the memory device. Each command that is configured to access the memory device is associated with an access timing parameter. The memory device includes an access parameter timer configured to measure an actual timing value of the access timing parameter, a spec register configured to provide a spec timing value defining an effective timing of the access timing parameter, a comparison circuit configured to compare the actual timing value and the spec timing value, and a mode register configured to store an access timing violation flag that is read by the host when the actual timing value deviates from the spec timing value by exceeding a predetermined range.

Abstract: There is provided an additive, containing magnesium silicate, for a secondary battery electrolyte and a preparation method therefor. The magnesium silicate has a mass ratio of 50 to 70 wt % of oxygen (O), 5 to 20 wt % of magnesium (Al), and 15 to 35 wt % of silicon (Si). The magnesium silicate has a surface area of 50 to 500 m2/g. The magnesium silicate has a pore size of 0.1 to 20 nm.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device. The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.

Abstract: There is provided an additive for secondary battery electrolyte, containing aluminum silicate. The aluminum silicate has a particle size of 200 nm to 20 ?m. The aluminum silicate has a mass ratio of 60 to 70 wt % of oxygen (O), 0.1 to 2.0 wt % of aluminum (Al), and 25 to 35 wt % of silicon (Si). The aluminum silicate has a surface area of 50 to 1,000 m2/g. The aluminum silicate has a pore size of 0.1 to 20 nm.

Abstract: An optical transceiver is provided. A transceiver optical sub-assembly included in the optical transceiver includes a package body, accommodating optical devices and including a front surface coupled to an optical signal terminal, and a feed-through structure closing a rear surface of the package body and an open portion provided at both side surfaces adjacent to the rear surface. A disposition portion where one end of a flexible printed circuit board (FPCB) is disposed is provided at a front surface of the feed-through structure. Feed-through electrodes bonded to FPCB electrodes provided at the one end of the FPCB are provided on a surface of the disposition portion. For precise alignment of the FPCB electrodes and the feed-through electrodes, a protrusion portion is provided at the one end of the FPCB, and an insertion groove into which the protrusion portion is inserted is formed in a front surface of the feed-through structure.

Abstract: A display device includes a pixel. The pixel is electrically connected to a first power line, a second power line, and a data line. The pixel includes a first transistor, and a capacitor electrically connected between a gate electrode of the first transistor and an electrode of the first transistor. In a plan view, the data line extends in a second direction. The first power line extends in a first direction intersecting the second direction and overlaps the data line and the gate electrode of the first transistor. The second power line extends in the second direction, overlaps the data line, and overlaps the gate electrode of the first transistor.

Abstract: An organic light emitting display device driven at a first driving frequency or a second driving frequency lower than the first driving frequency includes pixels coupled to first scan lines, second scan lines, and data lines, a first scan driver configured to supply scan signals to the first scan lines during a first period and a second period in one frame period, when the organic light emitting display device is driven at the second driving frequency, a second scan driver configured to supply scan signals to the second scan lines during the first period, when the organic light emitting display device is driven at the second driving frequency, and a data driver configured to supply a data signal to the data lines during the first period.

Abstract: A shoe management device may have a housing having a body to define an inner space and a cover to open or close the body to allow access to the inner space. Agitators may be provided at a bottom of the body, which may be configured to hold shoes, and the agitators may remove foreign matter from the shoes. An upper portion of the body may have an air generator configured to blow air toward the shoes to remove foreign matter. In addition, moisture and germs inside the shoe may be removed by hot air, ultraviolet light, and plasma ions provided by a care assembly provided inside of the body and configured to be at least partially inserted into the shoes.

Abstract: A display apparatus includes a substrate including a display area for displaying an image, a first thin film transistor in the display area and including a first semiconductor layer having a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a first interlayer insulating layer covering the first gate electrode and having a first contact hole extending therethrough, and a second thin film transistor on the first interlayer insulating layer and including a second semiconductor layer having an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer. A portion of the second semiconductor layer extends into a first contact hole and is electrically connected to the first semiconductor layer.

Abstract: A dual slot die coater according to the present disclosure is a dual slot die coater including a lower slot and an upper slot, for extrusion coating of an electrode active material slurry on a surface of a continuously moving current collector through at least one of the lower slot or the upper slot, and the dual slot die coater includes a lower plate, an intermediate plate positioned on the lower plate and an upper plate positioned on the intermediate plate, the lower slot being formed between the lower plate and the intermediate plate, and the upper slot being formed between the intermediate plate and the upper plate, wherein the lower plate, the intermediate plate and the upper plate have a lower die lip, an intermediate die lip and an upper die lip, each forming an front end with respect to the current collector, respectively, and a thickness of the lower die lip is larger than a thickness of the upper die lip and a thickness of the intermediate die lip.

Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.

Abstract: Disclosed is a test dummy including: a dummy body, a reservoir fixed to the dummy body and having an internal space for storing a fluid, a tube unit having a flow path through which the fluid stored in the reservoir circulates, and a heating unit configured to heat the fluid.