Patents by Inventor Kyung-Hwan Lee

Kyung-Hwan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12048150
    Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: July 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Il Gweon Kim, Hyun Cheol Kim, Hyeoung Won Seo, Sung Won Yoo, Jae Ho Hong
  • Publication number: 20240242884
    Abstract: A multilayer electronic component includes a dielectric layer and internal electrodes; wherein the dielectric layer includes a rare earth element, Mn, and Ti. The rare earth element includes a first rare earth element including Dy and Tb, and a second rare earth element including a rare earth element different from the first rare earth element. The number of moles of the rare earth element is defined as RE, the number of moles of Dy is defined as A1, the number of moles of Tb is defined as A2 based on 100 moles of Ti included in the dielectric layer, and 0.5 mol?RE?0.9 mol and 1<A2/A1 are satisfied. The number of moles of the second subcomponent element based on 100 moles of Ti included in the dielectric layer is 0.2 mole or more and 0.5 mole or less.
    Type: Application
    Filed: September 11, 2023
    Publication date: July 18, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon KWON, Hyoung Uk KIM, Kyung Sik KIM, Ji Su HONG, Seung In BAIK, Min Young CHOI, Si Taek PARK, Jong Hwan LEE, Jae Sung PARK
  • Publication number: 20240189747
    Abstract: An antibacterial filter, a method for manufacturing the filter, and an air purifier comprising the filter. The antibacterial filter contains a specific range of active copper particles bound to the surface of fibers, and thus can effectively prevent microorganisms, such as bacteria, fungi, and viruses, harmful to the human body, from proliferating on or contaminating the filter surface, and further improve antibacterial performance and sustained antibacterial performance. Additionally, when the antimicrobial filter is applied to an air purifier, it is possible to supply purified air and, at the same time, further improve the durability and lifetime characteristics of the filter.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 13, 2024
    Applicant: COWAY Co., Ltd.
    Inventors: Hyun Jun YUN, Hyun Kyu LEE, Hu Min LEE, Jong Cheol KIM, Byong Hyoek LEE, Kyung Hwan LEE
  • Patent number: 11963364
    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok Han Park, Yong Seok Kim, Hui-Jung Kim, Satoru Yamada, Kyung Hwan Lee, Jae Ho Hong, Yoo Sang Hwang
  • Patent number: 11903184
    Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: February 13, 2024
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Il Gweon Kim, Hui-Jung Kim, Min Hee Cho, Jae Ho Hong
  • Publication number: 20230363166
    Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 9, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kohji KANAMORI, Yong Seok KIM, Kyung Hwan LEE, Jun Hee LIM, Jee Hoon HAN
  • Patent number: 11812293
    Abstract: A method for operating a terminal in a wireless communication system is provided. The method includes at least one of transmitting data to and receiving data from a primary cell using a first Radio Frequency (RF) path, and, when a secondary cell is deactivated, operating a second RF path to perform searching and measurement with respect to at least one target cell at a frequency different from a frequency of the primary cell.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Hee Lee, Byung-Wook Kim, Seong-Joon Kim, Jae-Ho Song, Myung-Hoon Yeon, Se-Jin Kim, Kyung-Hwan Lee
  • Publication number: 20230269501
    Abstract: An image sensor includes a photoelectric converter configured to convert received light into charges in response to the received light and provide the charges to a first node, a transfer transistor configured to provide a voltage of the first node to a floating diffusion node, a reset transistor configured to reset a voltage of the floating diffusion node to a driving voltage based on a reset signal, a source follower transistor configured to provide a unit pixel output based on the voltage of the floating diffusion node, a select transistor connected to the source follower transistor and gated with a selection signal to output the unit pixel output to the outside, and a ferroelectric capacitor connected to the floating diffusion node, wherein the ferroelectric capacitor is configured to adjust a conversion gain of the floating diffusion node based on a conversion gain mode of the ferroelectric capacitor, the conversion gain mode being a first conversion gain mode, a second conversion gain mode, or a third co
    Type: Application
    Filed: December 21, 2022
    Publication date: August 24, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Soon KANG, Hyun Cheol KIM, Woo Bin SONG, Kyung Hwan LEE
  • Patent number: 11729976
    Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: August 15, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Kanamori, Yong Seok Kim, Kyung Hwan Lee, Jun Hee Lim, Jee Hoon Han
  • Patent number: 11723290
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 8, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Seok Han Park, Satoru Yamada, Jae Ho Hong
  • Patent number: 11721684
    Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 8, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Kanamori, Hyun Mog Park, Yong Seok Kim, Kyung Hwan Lee, Jun Hee Lim, Jee Hoon Han
  • Patent number: 11711918
    Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: July 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Hyun Cheol Kim, Satoru Yamada, Sung Won Yoo, Jae Ho Hong
  • Patent number: 11655533
    Abstract: An exterior material of a home appliance having improved corrosion resistance and fingerprint resistance by changing a treatment method of a surface of the exterior material, and the home appliance including the same, and a manufacturing method therefor are provided. The method of manufacturing the exterior material of the home appliance, the method including applying a diamond like carbon (DLC) coating on the substrate to form a DLC coating layer; and conducting anti-fingerprint coating to form the anti-fingerprint coating on the DLC coating layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 23, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Seok Shin, Kwang Joo Kim, Young Deog Koh, Jin O Kwak, Da Hyun Byeoun, Young Min Yoo, Kyung Hwan Lee, Min Kyung Lee
  • Publication number: 20230124298
    Abstract: A manufacturing method of a home appliance including a hairline according to disclosed embodiment includes forming at least one plating layer on the base material, processing the transverse hairline on the upper surface of the plating layer by tilting the hairline processing wheel at a predetermined angle, and forming a coating layer on the hairline.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan LEE, Ji Young SONG, Kwang Joo KIM, In Hye HWANG, Jong Su OH
  • Publication number: 20230085459
    Abstract: An antimicrobial filter media, which includes a non-woven fabric; and an antimicrobial agent bound to the nonwoven fabric by a binder, the antimicrobial agent including silver sodium zirconium hydrogenphosphate and thiabendazole, and the silver sodium zirconium hydrogenphosphate and the thiabendazole are employed at a weight ratio of 1:1.5 to 1.5:1, to an air cleaner including the same, and to a process for preparing the same. The antimicrobial filter media includes silver sodium zirconium hydrogenphosphate and thiabendazole, as an antimicrobial agent, at a specific weight ratio. As a result, it is possible to effectively filter harmful microorganisms to supply purified air, to have excellent antibacterial, antiviral, and antifungal properties at the same time, and to further enhance the durability and lifespan characteristics by virtue of excellent filter damage prevention effect.
    Type: Application
    Filed: July 29, 2022
    Publication date: March 16, 2023
    Applicant: COWAY Co., Ltd.
    Inventors: Kyung Hwan LEE, Yoon Hyuck CHOI, Jong Cheol KIM
  • Publication number: 20230019055
    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 19, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seok Han PARK, Yong Seok KIM, Hui-Jung KIM, Satoru YAMADA, Kyung Hwan LEE, Jae Ho HONG, Yoo Sang HWANG
  • Patent number: 11469252
    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok Han Park, Yong Seok Kim, Hui-Jung Kim, Satoru Yamada, Kyung Hwan Lee, Jae Ho Hong, Yoo Sang Hwang
  • Publication number: 20220199625
    Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.
    Type: Application
    Filed: August 3, 2021
    Publication date: June 23, 2022
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Il Gweon Kim, Hui-Jung Kim, Min Hee Cho, Jae Ho Hong
  • Publication number: 20220157887
    Abstract: A three-dimensional semiconductor memory device is provided. The semiconductor memory device includes first horizontal conductive lines on a substrate in a first direction, each of the first horizontal conductive lines extending in a second direction different from the first direction, second horizontal conductive lines stacked on the substrate in the first direction, each of the second horizontal conductive lines extending in the second direction, a vertical conductive line between the first horizontal conductive line and the second horizontal conductive line and extending in the first direction, a plurality of first magnetic tunnel junction patterns between the vertical conductive line and each of the first horizontal conductive lines, and a plurality of second magnetic tunnel junction patterns between the vertical conductive lines and each of the second horizontal conductive lines.
    Type: Application
    Filed: July 20, 2021
    Publication date: May 19, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung Hwan LEE, Kwang Seok KIM, Yong Seok KIM, Il Gweon KIM, Kil Ho LEE
  • Publication number: 20220139948
    Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.
    Type: Application
    Filed: July 16, 2021
    Publication date: May 5, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung Hwan LEE, Yong Seok KIM, Il Gweon KIM, Hyun Cheol KIM, Hyeoung Won SEO, Sung Won YOO, Jae Ho HONG