Abstract: An image sensor includes a photoelectric converter configured to convert received light into charges in response to the received light and provide the charges to a first node, a transfer transistor configured to provide a voltage of the first node to a floating diffusion node, a reset transistor configured to reset a voltage of the floating diffusion node to a driving voltage based on a reset signal, a source follower transistor configured to provide a unit pixel output based on the voltage of the floating diffusion node, a select transistor connected to the source follower transistor and gated with a selection signal to output the unit pixel output to the outside, and a ferroelectric capacitor connected to the floating diffusion node, wherein the ferroelectric capacitor is configured to adjust a conversion gain of the floating diffusion node based on a conversion gain mode of the ferroelectric capacitor, the conversion gain mode being a first conversion gain mode, a second conversion gain mode, or a third co

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.

Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.

Abstract: An exterior material of a home appliance having improved corrosion resistance and fingerprint resistance by changing a treatment method of a surface of the exterior material, and the home appliance including the same, and a manufacturing method therefor are provided. The method of manufacturing the exterior material of the home appliance, the method including applying a diamond like carbon (DLC) coating on the substrate to form a DLC coating layer; and conducting anti-fingerprint coating to form the anti-fingerprint coating on the DLC coating layer.

Abstract: A manufacturing method of a home appliance including a hairline according to disclosed embodiment includes forming at least one plating layer on the base material, processing the transverse hairline on the upper surface of the plating layer by tilting the hairline processing wheel at a predetermined angle, and forming a coating layer on the hairline.

Abstract: An antimicrobial filter media, which includes a non-woven fabric; and an antimicrobial agent bound to the nonwoven fabric by a binder, the antimicrobial agent including silver sodium zirconium hydrogenphosphate and thiabendazole, and the silver sodium zirconium hydrogenphosphate and the thiabendazole are employed at a weight ratio of 1:1.5 to 1.5:1, to an air cleaner including the same, and to a process for preparing the same. The antimicrobial filter media includes silver sodium zirconium hydrogenphosphate and thiabendazole, as an antimicrobial agent, at a specific weight ratio. As a result, it is possible to effectively filter harmful microorganisms to supply purified air, to have excellent antibacterial, antiviral, and antifungal properties at the same time, and to further enhance the durability and lifespan characteristics by virtue of excellent filter damage prevention effect.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

Abstract: A three-dimensional semiconductor memory device is provided. The semiconductor memory device includes first horizontal conductive lines on a substrate in a first direction, each of the first horizontal conductive lines extending in a second direction different from the first direction, second horizontal conductive lines stacked on the substrate in the first direction, each of the second horizontal conductive lines extending in the second direction, a vertical conductive line between the first horizontal conductive line and the second horizontal conductive line and extending in the first direction, a plurality of first magnetic tunnel junction patterns between the vertical conductive line and each of the first horizontal conductive lines, and a plurality of second magnetic tunnel junction patterns between the vertical conductive lines and each of the second horizontal conductive lines.

Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

Abstract: A method of operating a terminal is provided. The method includes: selecting a first pattern as a pattern of a reception beam; searching for cells in the wireless communication system using the reception beam of the first pattern; determining a first candidate group including at least one candidate for a beam pattern pair with the first pattern of the reception beam, wherein each of the at least one candidate corresponds to a transmission beam pattern and a cell; determining whether to decode a physical broadcast channel received from a first candidate of the first candidate group; decoding the PBCH based on the determining; and selecting one of the transmission beam patterns for the beam pattern pair with the first pattern of the reception beam from the first candidate group based on the decoding.

Abstract: A vertical-type memory device includes: a first gate structure including first gate electrodes spaced apart from each other and stacked on a substrate; first channel structures penetrating through the first gate structure and being in contact with the substrate; a second gate structure including second gate electrodes spaced apart from each other and stacked on the first gate structure; and second channel structures penetrating through the second gate structure and being in contact with the first channel structures. The first channel structures each may include a first channel layer penetrating the first gate structure, and a first channel pad disposed on the first channel layer and including a first pad region including n-type impurities and a second pad region including p-type impurities.

Abstract: A passivation surface treatment method of stainless steel that improves corrosion resistance including in a brine environment without changing the appearance of the surface of stainless steel. A passivation surface treatment method for stainless steel includes: performing degreasing of stainless steel, performing electrolytic pickling where the stainless steel that underwent the degreasing is immersed in a pickling solution having phosphoric acid (H3PO4) and is connected to the anode and a voltage of about 0.5 to 5.0 V for about 10 seconds or more is applied, performing electrolytic degreasing of the stainless steel, and performing electrolytic passivation where the stainless steel that underwent the electrolytic degreasing is immersed in a passivation solution including dichromic acid and chromium sulfate and a voltage of about 0.5 to 5.0 V is applied for 5 seconds or more.

Abstract: A method for operating a terminal in a wireless communication system is provided. The method includes at least one of transmitting data to and receiving data from a primary cell using a first Radio Frequency (RF) path, and, when a secondary cell is deactivated, operating a second RF path to perform searching and measurement with respect to at least one target cell at a frequency different from a frequency of the primary cell.

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.