Abstract: An exterior material of a home appliance having improved corrosion resistance and fingerprint resistance by changing a treatment method of a surface of the exterior material, and the home appliance including the same, and a manufacturing method therefor are provided. The method of manufacturing the exterior material of the home appliance, the method including applying a diamond like carbon (DLC) coating on the substrate to form a DLC coating layer; and conducting anti-fingerprint coating to form the anti-fingerprint coating on the DLC coating layer.

Abstract: A vertical-type memory device includes: a first gate structure including first gate electrodes spaced apart from each other and stacked on a substrate; first channel structures penetrating through the first gate structure and being in contact with the substrate; a second gate structure including second gate electrodes spaced apart from each other and stacked on the first gate structure; and second channel structures penetrating through the second gate structure and being in contact with the first channel structures. The first channel structures each may include a first channel layer penetrating the first gate structure, and a first channel pad disposed on the first channel layer and including a first pad region including n-type impurities and a second pad region including p-type impurities.

Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

Abstract: A vertical memory device includes a stacked structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers extending in a direction perpendicular to an upper surface of the substrate on a first side surface of the stacked structure and spaced apart from each other in a direction parallel to the upper surface of the substrate, and a common source layer disposed between the stacked structure and the substrate and contacting the channel layers.

Abstract: A vertical memory device includes gate electrodes on a substrate and a first structure. The gate electrodes may be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction, and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs) therein.

Abstract: A memory device includes memory cells, the memory cells each including a first gate, a second gate electrically isolated from the first gate, a first gate insulating layer including a data storage layer having a ferroelectric material and disposed between the first gate and a channel region, a second gate insulating layer disposed between the second gate and the channel region, a first switching cell connected between the memory cells and a source line, and a second switching cell connected between the memory cells and a bit line. The second switching cell includes a third gate, a fourth gate, a third gate insulating layer not including a data storage layer having the ferroelectric material and the third gate disposed between the third gate and the channel region, and a fourth gate insulating layer disposed between the fourth gate and the channel region.

Abstract: A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.

Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

Abstract: A method for operating a terminal in a wireless communication system is provided. The method includes at least one of transmitting data to and receiving data from a primary cell using a first Radio Frequency (RF) path, and, when a secondary cell is deactivated, operating a second RF path to perform searching and measurement with respect to at least one target cell at a frequency different from a frequency of the primary cell.

Abstract: Provided is an oven including a door for opening and closing a cooking chamber, in which a locking portion provided on a glass holder for supporting an outer glass moves along a locking slot provided in a chassis to be fitted to the locking slot, so that assembly of the door is facilitated.

Abstract: A method of operating a terminal is provided. The method includes: selecting a first pattern as a pattern of a reception beam; searching for cells in the wireless communication system using the reception beam of the first pattern; determining a first candidate group including at least one candidate for a beam pattern pair with the first pattern of the reception beam, wherein each of the at least one candidate corresponds to a transmission beam pattern and a cell; determining whether to decode a physical broadcast channel received from a first candidate of the first candidate group; decoding the PBCH based on the determining; and selecting one of the transmission beam patterns for the beam pattern pair with the first pattern of the reception beam from the first candidate group based on the decoding.

Abstract: Disclosed herein is a clock. The clock includes: a first belt; an hour axis unit comprising first and second rotation axis spaced apart from each other by a predetermined distance and being rotable; and an hour hand configured to point a position of the hour axis unit, wherein the first belt makes revolutions by being engaged with the first and second rotation axis.

Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.

Abstract: In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.

Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

Abstract: A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.

Abstract: A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.

Abstract: A passivation surface treatment method of stainless steel that improves corrosion resistance including in a brine environment without changing the appearance of the surface of stainless steel. A passivation surface treatment method for stainless steel includes: performing degreasing of stainless steel, performing electrolytic pickling where the stainless steel that underwent the degreasing is immersed in a pickling solution having phosphoric acid (H3PO4) and is connected to the anode and a voltage of about 0.5 to 5.0 V for about 10 seconds or more is applied, performing electrolytic degreasing of the stainless steel, and performing electrolytic passivation where the stainless steel that underwent the electrolytic degreasing is immersed in a passivation solution including dichromic acid and chromium sulfate and a voltage of about 0.5 to 5.0 V is applied for 5 seconds or more.

Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.

Abstract: An air purifying unit in which leakage of air flowing between a filter and a blowing fan is significantly reduced, and an air cleaning/ventilation device including the same, are provided. In addition, there are an air cleaning/ventilation device detachably installed in a window, used as a ventilation device, and used as an indoor air cleaning device.