Patents by Inventor Kyung Jin Byun
Kyung Jin Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10013310Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.Type: GrantFiled: August 19, 2016Date of Patent: July 3, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jin Ho Han, Young-Su Kwon, Kyoung Seon Shin, Kyung Jin Byun, Nak Woong Eum
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Patent number: 10002009Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.Type: GrantFiled: January 17, 2017Date of Patent: June 19, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Jin Lee, Hyeong Uk Jang, Kyung Jin Byun, Nak Woong Eum
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Patent number: 10003808Abstract: An encoding apparatus in accordance with an embodiment of the present invention includes: an encoder configured to request for storage of an original frame; a frame processing unit configured to generate an encoded frame having the original framed encoded therein; and a frame memory configured to store the encoded frame. Here, the frame processing unit is configured to generate the original frame by encoding the encoded frame stored in the frame memory according to a request of the encoder, and the encoder is configured to perform encoding according to the original frame.Type: GrantFiled: May 27, 2015Date of Patent: June 19, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Mo Park, Kyung-Jin Byun, Nak-Woong Eum
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Patent number: 9859889Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.Type: GrantFiled: January 24, 2017Date of Patent: January 2, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Woojoo Lee, Young-Su Kwon, Kyung Jin Byun, Jin Ho Han, Nak Woong Eum
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Patent number: 9836401Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.Type: GrantFiled: July 28, 2016Date of Patent: December 5, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Jin Lee, Kyung Jin Byun, Nak Woong Eum
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Publication number: 20170347150Abstract: Provided is a video providing system. The video providing system includes a memory configured to store device information of a display device, an analyzer configured to receive an original video from the outside and analyze images in the original video, and a processor configured to generate, from the original video, video streams according to a streaming mode and control signals of the display device respectively corresponding to the video streams, based on device information of a display device and analysis information from the analyzer, and provide the video streams and the control signals to the display device.Type: ApplicationFiled: May 4, 2017Publication date: November 30, 2017Applicant: Electronics and Telecommunications Research InstituteInventors: Woojoo LEE, Sukho LEE, Kyung Jin BYUN, Sung Weon KANG
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Publication number: 20170262011Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.Type: ApplicationFiled: February 14, 2017Publication date: September 14, 2017Applicant: Electronics and Telecommunications Research InstituteInventors: Young-Su KWON, Kyung Jin BYUN, Nak Woong EUM
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Publication number: 20170255554Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.Type: ApplicationFiled: August 19, 2016Publication date: September 7, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jin Ho HAN, Young-Su KWON, Kyung Jin BYUN, Nak Woong EUM
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Publication number: 20170257632Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.Type: ApplicationFiled: August 9, 2016Publication date: September 7, 2017Inventors: Sukho LEE, Kyung Jin BYUN, Nak Woong EUM
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Publication number: 20170255520Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.Type: ApplicationFiled: August 19, 2016Publication date: September 7, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jin Ho HAN, Young-Su KWON, Kyoung Seon SHIN, Kyung Jin BYUN, Nak Woong EUM
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Publication number: 20170222648Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.Type: ApplicationFiled: January 24, 2017Publication date: August 3, 2017Applicant: Electronics and Telecommunications Research InstituteInventors: Woojoo LEE, Young-Su KWON, Kyung Jin BYUN, Jin Ho HAN, Nak Woong EUM
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Publication number: 20170206102Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.Type: ApplicationFiled: January 17, 2017Publication date: July 20, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Jin LEE, Hyeong Uk JANG, Kyung Jin BYUN, Nak Woong EUM
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Publication number: 20170192885Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.Type: ApplicationFiled: July 28, 2016Publication date: July 6, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Jin LEE, Kyung Jin BYUN, Nak Woong EUM
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Patent number: 9632894Abstract: The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.Type: GrantFiled: April 2, 2015Date of Patent: April 25, 2017Assignee: Electronics and Telecommunications Research InstituteInventors: Jin-Ho Han, Young-Su Kwon, Kyung-Jin Byun
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Patent number: 9529654Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.Type: GrantFiled: November 19, 2014Date of Patent: December 27, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Young Su Kwon, Jin Ho Han, Kyung Jin Byun
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Publication number: 20160366434Abstract: Disclosed herein are motion estimation apparatus and method. The motion estimation apparatus may determine an SAD of a coding unit in a current image and calculate an average SAD of the current image. The motion estimation apparatus may compare the SAD of the coding unit with the average SAD of the current image, and determine the number of one or more previous images to be used for motion estimation of the coding unit based on the results of comparison.Type: ApplicationFiled: January 27, 2016Publication date: December 15, 2016Inventors: Seong-Mo PARK, Kyung-Jin BYUN, Nak-Woong EUM
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Patent number: 9510021Abstract: Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.Type: GrantFiled: May 23, 2014Date of Patent: November 29, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seunghyun Cho, Hyun Mi Kim, Kyung Jin Byun, Nak Woong Eum
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Patent number: 9438927Abstract: A motion estimation apparatus and method are disclosed. The motion estimation apparatus includes processing element (PE) array units, sub-SAD calculation units, motion vector calculation units, and a minimum motion vector selector. The PE array units each perform parallel processing for each of the three types of coding units. The sub-SAD calculation units calculate respective SAD values for the three types of coding units. The motion vector calculation units calculate respective motion vectors for the three types of coding units. The minimum motion vector selector selects a minimum motion vector from among the motion vectors.Type: GrantFiled: March 18, 2014Date of Patent: September 6, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Mo Park, Kyung-Jin Byun, Nak-Woong Eum
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Patent number: 9398309Abstract: An apparatus and method for skipping fractional motion estimation (FME) in high efficiency video coding (HEVC) are disclosed. The apparatus includes a current sum of absolute differences (SAD) acquisition unit, a redundancy determination unit, and a motion estimation skip unit. The SAD acquisition unit acquires the SAD from an integer motion estimation (IME) unit when the IME unit performs IME on a coding tree block (CTB). The redundancy determination unit determines whether or not the CTB is an estimated redundant block using the current SAD. The motion estimation skip unit provides an FME unit with an FME skip signal of the CTB depending on whether or the CTB is an estimated redundant block.Type: GrantFiled: April 29, 2014Date of Patent: July 19, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Mo Park, Seung-Hyun Cho, Hyun-Mi Kim, Kyung-Jin Byun, Nak-Woong Eum
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Publication number: 20160057435Abstract: An encoding apparatus in accordance with an embodiment of the present invention includes: an encoder configured to request for storage of an original frame; a frame processing unit configured to generate an encoded frame having the original framed encoded therein; and a frame memory configured to store the encoded frame. Here, the frame processing unit is configured to generate the original frame by encoding the encoded frame stored in the frame memory according to a request of the encoder, and the encoder is configured to perform encoding according to the original frame.Type: ApplicationFiled: May 27, 2015Publication date: February 25, 2016Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Mo PARK, Kyung-Jin BYUN, Nak-Woong EUM