Abstract: An apparatus for processing a register window overflow and underflow includes register windows each configured to include local registers and incoming registers, dedicated internal memories configured to store contents of the local registers and the incoming registers for each word, dedicated data buses configured to connect the local registers and the incoming registers and the respective dedicated internal memories, a memory word counter configured to perform counting in order to determine whether or not there is a storage space of a word unit in the dedicated internal memories, and a logic block configured to control an operation of the dedicated data buses when one of a window overflow and a window underflow is generated based on the count value of the memory word counter.

Abstract: The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.

Abstract: Disclosed herein is an apparatus for fast Sample Adaptive Offset filtering based on a convolution method, for decoding of a video. According an embodiment, the apparatus may include: an input stream provider for sequentially providing a window buffer with pixels read from a buffer that stores input data related to an SAO filter; a window buffer for defining the provided pixels as one or more windows, and for delivering the pixels on a defined window basis to one or more calculation logics; and one or more calculation logics for calculating an offset for the pixels input on the window basis, and for outputting a corrected pixel by adding the calculated offset to a target pixel.

Abstract: An apparatus and method for determining a discrete cosine transform (DCT) size based on a transform depth are disclosed herein. The apparatus for determining a DCT size based on a transform depth includes a prediction mode determination unit, a transform unit (TU) generation unit, and a DCT performance unit. The prediction mode determination unit determines a prediction mode in order to determine a DCT size at the root location of a coding unit (CU) present in a coding tree unit (CTU). The transform unit (TU) generation unit partitions the CU into transform units (TUs) based on a residual quad tree (RQT). The DCT performance unit performs a DCT based on the TUs.

Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.

Abstract: Disclosed is a residual signal inter-channel intra prediction encoding method between a residual signal of a luminance component of an image and a residual signal of a chrominance component thereof. It is possible to improve an intra prediction encoding performance when the inter-channel prediction is performed between residual signal of the luminance component and the chrominance component of HEVC, and derive a prediction coefficient for linear prediction at a high speed while the quadtree block structure of the HEVC is not changed. In addition, it is advantageous to avoid degradation in inter-channel prediction performance, which is caused when quadtree block structures of prediction units (PUs) of the luminance component and the chrominance component are different.

Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.

Abstract: Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.

Abstract: An apparatus and method for controlling a multi-core SoC including a main core and at least one sub-core are disclosed. The apparatus includes a determination unit, a storage unit, and a control unit. The determination unit determines whether or not to drive the sub-core by taking the performance or power of the multi-core SoC into consideration. The storage unit stores state information including a register of the main core or the sub-core in accordance with a determination of the determination unit. The control unit performs control so that the main core and the sub-core execute a sub-task, that is, a task of the sub-core, through exchange by sharing the state information.

Abstract: An apparatus and method for skipping fractional motion estimation (FME) in high efficiency video coding (HEVC) are disclosed. The apparatus includes a current sum of absolute differences (SAD) acquisition unit, a redundancy determination unit, and a motion estimation skip unit. The SAD acquisition unit acquires the SAD from an integer motion estimation (IME) unit when the IME unit performs IME on a coding tree block (CTB). The redundancy determination unit determines whether or not the CTB is an estimated redundant block using the current SAD. The motion estimation skip unit provides an FME unit with an FME skip signal of the CTB depending on whether or the CTB is an estimated redundant block.

Abstract: A motion estimation apparatus and method are disclosed. The motion estimation apparatus includes processing element (PE) array units, sub-SAD calculation units, motion vector calculation units, and a minimum motion vector selector. The PE array units each perform parallel processing for each of the three types of coding units. The sub-SAD calculation units calculate respective SAD values for the three types of coding units. The motion vector calculation units calculate respective motion vectors for the three types of coding units. The minimum motion vector selector selects a minimum motion vector from among the motion vectors.

Abstract: Disclosed herein are an apparatus and a method of providing recompression of a video capable of recompressing and transmitting flags of data having an association with neighboring data in a video block and an original video by a simple logic. To this end, the apparatus of providing recompression of a video includes: a recompressing unit recompressing a compressed video frame based on information obtained by comparing a selected block selected from the compressed video frame and an adjacent block adjacent to the selected block with each other; and a frame memory controlling unit storing the recompressed video frame in a frame memory. Therefore, a hardware volume may be decreased while original video data are maintained.

Abstract: An apparatus for processing a register window overflow and underflow includes register windows each configured to include local registers and incoming registers, dedicated internal memories configured to store contents of the local registers and the incoming registers for each word, dedicated data buses configured to connect the local registers and the incoming registers and the respective dedicated internal memories, a memory word counter configured to perform counting in order to determine whether or not there is a storage space of a word unit in the dedicated internal memories, and a logic block configured to control an operation of the dedicated data buses when one of a window overflow and a window underflow is generated based on the count value of the memory word counter.

Abstract: A method for decoding segmented speech frames includes: generating parameters of a segmented current speech frame by using parameters of a segmented previous speech frame; and decoding a speech frame by using the parameters of the current speech frame, which are generated in the generating of the parameters of the segmented current speech frame.

Abstract: Provided are an apparatus for controlling power management of a DSP (Digital Signal Processor) and a power management system and method using the same. The power management system includes a command decoding device for decoding a program into which a PSM (Power Saving Mode) command and a general command are inserted and transmitting module information required for execution of a corresponding command to a power management control apparatus at the time of decoding the corresponding command; a pipeline control device for blocking and restarting the transmission of data through a pipeline upon receipt of a pipeline control signal (pipeline stall) from the power management control device; and the power management control apparatus for controlling power in respective modules by setting/resetting corresponding bits of a PSM status register and a PSM flag register in accordance with the PSM command and the general command decoded in the command decoding device.

Abstract: Disclosed are an arithmetic apparatus including MAC calculation, and a DSP structure and a filtering method using the same. The arithmetic apparatus includes: first and second registers storing one or more pieces of n-bit data (n is a natural number); a third register storing one or more pieces of 2n bit data; a multiplier having a first input terminal connected to the first register, a second input terminal connected to the second and third registers, and multiplying an input value of the first input terminal and that of the second input terminal; and an arithmetic-logic unit (ALU) having a first input terminal connected to an output terminal of the multiplier and a second input terminal feedback-connected to an output terminal, adding an input value of the first terminal and that of the second terminal, and having the output terminal connected to the third register.

Abstract: A waveform interpolation speech coding apparatus and method for reducing complexity thereof are disclosed. The waveform interpolation speech coding apparatus includes: a waveform interpolation encoding unit for receiving a speech signal, calculating parameters for a waveform interpolation from the received speech signal, and quantizing the calculating parameters; and a realignment parameter calculating unit for restoring a characteristic waveform (CW) using the quantized parameter, calculating a realignment parameter that maximizes a cross-correlation among consecutive CWs for the restored CW.

Abstract: Provided is a method for converting a dimension of a vector. The vector dimension conversion method for vector quantization includes the steps of: extracting a specific parameter having a pitch period from an input speech signal and then generating a vector of a dimension that varies according to the pitch period; dividing an entire frequency domain of the generated vector of the variable dimension into at least two frequency domains; and converting the vector of the variable dimension into vectors of mutually different fixed dimensions according to the divided frequency domains. Thereby, not only an error due to the vector dimension conversion is suppressed but codebook memory required for the vector quantization is effectively reduced.

Abstract: Provided are a flexible bit rate code vector generation method and a wideband vocoder employing the same. This invention implements a flexible bit rate by getting three code vectors which are composed of 24, 16, and 8 pulses, at a time in a search process, through improvement of an algebraic codebook search process in a wideband AMR-WB vocoder. The method includes the steps of: performing a preprocess, wherein the preprocess divides a sub-frame by tracks and decides a pulse position having a maximum value in each track; among a plurality of pulses to be searched, fixing a same number of pulses as the tracks to the position with the maximum value of each track sequentially, and searching optimal positions having a minimum error with a target signal by combining two pulses in two consecutive tracks for the remaining pulses; and creating a code vector with flexible bit rate.

Abstract: Provided are an apparatus for controlling power management of a DSP (Digital Signal Processor) and a power management system and method using the same. The power management system includes a command decoding device for decoding a program into which a PSM (Power Saving Mode) command and a general command are inserted and transmitting module information required for execution of a corresponding command to a power management control apparatus at the time of decoding the corresponding command; a pipeline control device for blocking and restarting the transmission of data through a pipeline upon receipt of a pipeline control signal (pipeline stall) from the power management control device; and the power management control apparatus for controlling power in respective modules by setting/resetting corresponding bits of a PSM status register and a PSM flag register in accordance with the PSM command and the general command decoded in the command decoding device.