Patents by Inventor KyungOe Kim
KyungOe Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929334Abstract: A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.Type: GrantFiled: October 12, 2020Date of Patent: March 12, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, Jr., KyungOe Kim, TaeKeun Lee
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Publication number: 20240021566Abstract: A semiconductor device has a semiconductor die with a sensitive area. A dam wall is formed over the semiconductor die proximate to the sensitive area. In one embodiment, the dam wall has a vertical segment and side wings. The dam wall can have a plurality of rounded segments integrated with a plurality of vertical segments as a unitary body. Alternatively, the dam wall has a plurality of separate vertical segments arranged in two or more overlapping rows. A plurality of conductive posts is formed over the semiconductor die. An electrical component is disposed over the semiconductor die. The semiconductor die and electrical component are disposed over a substrate. An insulating layer is formed over the substrate outside the dam wall. An underfill material is deposited between the semiconductor die and substrate. The dam wall and insulating layer inhibit the underfill material from contacting any portion of the sensitive area.Type: ApplicationFiled: July 15, 2022Publication date: January 18, 2024Applicant: STATS ChipPAC Pte. Ltd.Inventors: WooSoon Kim, JoonYoung Choi, YoungCheol Kim, KyungOe Kim
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Patent number: 11823973Abstract: A semiconductor device has a substrate and two semiconductor die disposed over the substrate. A thermal interface material is disposed over the semiconductor die. A conductive epoxy is disposed on a ground pad of the substrate. A lid is disposed over the semiconductor die. The lid includes a sidewall over the ground pad between the semiconductor die. The lid physically contacts the conductive epoxy and thermal interface material.Type: GrantFiled: October 15, 2021Date of Patent: November 21, 2023Assignee: STATS ChipPAC Pte. Ltd.Inventors: DongSam Park, KyungOe Kim, WooJin Lee
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Patent number: 11817357Abstract: A semiconductor device is formed by providing a semiconductor die. A laser-assisted bonding (LAB) assembly is disposed over the semiconductor die. The LAB assembly includes an infrared (IR) camera. The IR camera is used to capture an image of the semiconductor die. Image processing is performed on the image to identify corners of the semiconductor die. Regions of interest (ROI) are identified in the image relative to the corners of the semiconductor die. Parameters can be used to control the size and location of the ROI relative to the respective corners. The ROI are monitored for temperature using the IR camera while LAB is performed.Type: GrantFiled: June 9, 2021Date of Patent: November 14, 2023Assignee: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, Jr., KyungOe Kim
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Publication number: 20230307414Abstract: A semiconductor device has a semiconductor die and a support tape disposed over a back surface of the semiconductor die opposite an active surface of the semiconductor die. A portion of the back surface of the semiconductor wafer is removed to reduce its thickness. The semiconductor die is part of a semiconductor wafer, and the wafer is singulated to provide the semiconductor die with the support tape disposed on the back surface of the semiconductor die. The support tape can be a polyimide tape. A dicing tape is disposed over the support tape. The semiconductor die is disposed over a substrate. A laser emission is projected onto the semiconductor die to bond the semiconductor die to the substrate. The support tape provides stress relief to avoid warpage of the semiconductor die during the laser emission. The support tape is removed from the back surface of the semiconductor die.Type: ApplicationFiled: May 11, 2023Publication date: September 28, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, JR., KyungOe Kim
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Publication number: 20230260865Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: KyungOe Kim, Wagno Alves Braganca, JR., DongSam Park
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Patent number: 11688718Abstract: A semiconductor device has a semiconductor die and a support tape disposed over a back surface of the semiconductor die opposite an active surface of the semiconductor die. A portion of the back surface of the semiconductor wafer is removed to reduce its thickness. The semiconductor die is part of a semiconductor wafer, and the wafer is singulated to provide the semiconductor die with the support tape disposed on the back surface of the semiconductor die. The support tape can be a polyimide tape. A dicing tape is disposed over the support tape. The semiconductor die is disposed over a substrate. A laser emission is projected onto the semiconductor die to bond the semiconductor die to the substrate. The support tape provides stress relief to avoid warpage of the semiconductor die during the laser emission. The support tape is removed from the back surface of the semiconductor die.Type: GrantFiled: September 7, 2021Date of Patent: June 27, 2023Assignee: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, Jr., KyungOe Kim
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Patent number: 11670563Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.Type: GrantFiled: June 24, 2021Date of Patent: June 6, 2023Assignee: STATS ChipPAC Pte. Ltd.Inventors: KyungOe Kim, Wagno Alves Braganca, Jr., DongSam Park
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Publication number: 20230125546Abstract: A semiconductor device has an interposer. A first semiconductor die with a photonic portion is disposed over the interposer. The photonic portion extends outside a footprint of the interposer. The interposer and first semiconductor die are disposed over a substrate. An encapsulant is deposited between the interposer and substrate. The photonic portion remains exposed from the encapsulant.Type: ApplicationFiled: October 27, 2021Publication date: April 27, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: KyungOe Kim, YoungCheol Kim, HeeSoo Lee
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Publication number: 20230119942Abstract: A semiconductor device has a substrate and two semiconductor die disposed over the substrate. A thermal interface material is disposed over the semiconductor die. A conductive epoxy is disposed on a ground pad of the substrate. A lid is disposed over the semiconductor die. The lid includes a sidewall over the ground pad between the semiconductor die. The lid physically contacts the conductive epoxy and thermal interface material.Type: ApplicationFiled: October 15, 2021Publication date: April 20, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: DongSam Park, KyungOe Kim, WooJin Lee
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Publication number: 20230077132Abstract: A semiconductor device has a semiconductor die and a support tape disposed over a back surface of the semiconductor die opposite an active surface of the semiconductor die. A portion of the back surface of the semiconductor wafer is removed to reduce its thickness. The semiconductor die is part of a semiconductor wafer, and the wafer is singulated to provide the semiconductor die with the support tape disposed on the back surface of the semiconductor die. The support tape can be a polyimide tape. A dicing tape is disposed over the support tape. The semiconductor die is disposed over a substrate. A laser emission is projected onto the semiconductor die to bond the semiconductor die to the substrate. The support tape provides stress relief to avoid warpage of the semiconductor die during the laser emission. The support tape is removed from the back surface of the semiconductor die.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, JR., KyungOe Kim
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Publication number: 20220415744Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: STATS ChipPAC Pte. Ltd.Inventors: KyungOe Kim, Wagno Alves Braganca, JR., DongSam Park
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Publication number: 20220399236Abstract: A semiconductor device is formed by providing a semiconductor die. A laser-assisted bonding (LAB) assembly is disposed over the semiconductor die. The LAB assembly includes an infrared (IR) camera. The IR camera is used to capture an image of the semiconductor die. Image processing is performed on the image to identify corners of the semiconductor die. Regions of interest (ROI) are identified in the image relative to the corners of the semiconductor die. Parameters can be used to control the size and location of the ROI relative to the respective corners. The ROI are monitored for temperature using the IR camera while LAB is performed.Type: ApplicationFiled: June 9, 2021Publication date: December 15, 2022Applicant: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, JR., KyungOe Kim
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Publication number: 20210296268Abstract: A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.Type: ApplicationFiled: October 12, 2020Publication date: September 23, 2021Applicant: STATS ChipPAC Pte. Ltd.Inventors: Wagno Alves Braganca, JR., KyungOe Kim, TaeKeun Lee
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Patent number: 10109587Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.Type: GrantFiled: August 2, 2016Date of Patent: October 23, 2018Assignee: STATS ChipPAC Pte. Ltd.Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
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Patent number: 9773685Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact or near proximity of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: June 21, 2012Date of Patent: September 26, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 9412624Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.Type: GrantFiled: June 26, 2014Date of Patent: August 9, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
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Patent number: 9373573Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: June 16, 2014Date of Patent: June 21, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Publication number: 20150318259Abstract: An integrated circuit packaging system, and a method of manufacture thereof, includes: an integrated circuit; a substrate having a substrate contact; an internal interconnect between the substrate and the integrated circuit, the internal interconnect is a no-reflow connection directly on the substrate contact and the integrated circuit; and an encapsulation over the internal interconnect.Type: ApplicationFiled: April 27, 2015Publication date: November 5, 2015Inventors: KyungOe Kim, Seong Won Park, MinJung Kim, ChangHwan Kim, ByungHyun Kwak, WanIl Lee
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Patent number: 9093278Abstract: A method of manufacture of an integrated circuit packaging system including: heating a support structure having a conductive pad and an organic surface protection layer on the conductive pad; removing the organic surface protection layer from the conductive pad by a plasma process with a two-step method, the two-step method includes a first step with a dioxygen and a second step with a dihydrogen, wherein the second step immediately follows the first step; and forming an underfill over the conductive pad.Type: GrantFiled: December 20, 2013Date of Patent: July 28, 2015Assignee: STATS ChipPAC Ltd.Inventors: JoonYoung Choi, Seong Won Park, KyungOe Kim, Hun Teak Lee, SungWon Cho