Patents by Inventor KyungOe Kim
KyungOe Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8859342Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit.Type: GrantFiled: December 14, 2011Date of Patent: October 14, 2014Assignee: STATS ChipPAC Ltd.Inventors: Oh Han Kim, Haengcheol Choi, KyungOe Kim
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Publication number: 20140291839Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: ApplicationFiled: June 16, 2014Publication date: October 2, 2014Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 8810029Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: February 6, 2012Date of Patent: August 19, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Publication number: 20130154079Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Inventors: Oh Han Kim, Haengcheol Choi, KyungOe Kim
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Publication number: 20120273943Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact or near proximity of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: ApplicationFiled: June 21, 2012Publication date: November 1, 2012Applicant: STATS CHIPPAC, LTD.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 8288205Abstract: The present invention is a method of manufacture of a package-in-package system, comprising: providing a bottom internal stacking module incorporating a semiconductor die and a package substrate, attaching an internal stiffening module, with a die receptacle, on the bottom internal stacking module, and attaching a top internal stacking module incorporating a further semiconductor die and a further package substrate upside-down on the internal stiffening module.Type: GrantFiled: March 19, 2008Date of Patent: October 16, 2012Assignee: Stats Chippac Ltd.Inventors: Seong Bo Shim, KyungOe Kim, Yong Hee Kang
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Patent number: 8216930Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: December 21, 2009Date of Patent: July 10, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Publication number: 20120133043Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: ApplicationFiled: February 6, 2012Publication date: May 31, 2012Applicant: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, Taewoo Kang
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Patent number: 8129841Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: November 24, 2009Date of Patent: March 6, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 8124520Abstract: An integrated circuit mount system includes an integrated circuit, a solder mask for the integrated circuit, and a solder mask pad on the substrate with the solder mask.Type: GrantFiled: July 10, 2006Date of Patent: February 28, 2012Assignee: Stats Chippac Ltd.Inventors: KyungOe Kim, Haengcheol Choi, Kyung Moon Kim, Rajendra D. Pendse
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Patent number: 8115301Abstract: Methods for fabricating flip-chips are disclosed. In an exemplary method, a flip-chip is mounted, active-surface downward, onto a substrate such that a back-side of the flip-chip is facing upward and electrical connections are made between the chip and an upward-facing surface of the substrate. An adhesive is applied to selected regions not occupied by the flip-chip. A heat-spreader is applied to contact the applied adhesive without contacting the back-side of the flip-chip, leaving a gap between the heat-spreader and the back-side of the flip-chip. The heat-spreader defines at least one through-hole that, when the heat-spreader is placed, is within a perimeter of the flip-chip. The adhesive is cured, and a thermal-insulating material (TIM) is applied through the at least one through-hole so as to fill the gap with the TIM. The methods substantially reduce the probability of die damage that otherwise occurs during attachment of heat-spreaders.Type: GrantFiled: November 17, 2006Date of Patent: February 14, 2012Assignee: STATS ChipPAC, Inc.Inventors: KyungOe Kim, YoungJoon Kim, HyunSoo Shin
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Patent number: 8018052Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.Type: GrantFiled: June 29, 2007Date of Patent: September 13, 2011Assignee: Stats Chippac Ltd.Inventors: KyungOe Kim, Taewoo Kang, HyunSu Shin
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Patent number: 7851345Abstract: A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.Type: GrantFiled: March 19, 2008Date of Patent: December 14, 2010Assignee: STATS ChipPAC, Ltd.Inventors: SeongBo Shim, KyungOe Kim, YongHee Kang
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Publication number: 20100099222Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: ApplicationFiled: December 21, 2009Publication date: April 22, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Rajendra D. Pendse, KyungOe Kim, Taewoo Kang
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Publication number: 20100065966Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: ApplicationFiled: November 24, 2009Publication date: March 18, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 7659633Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: December 14, 2006Date of Patent: February 9, 2010Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, Taewoo Kang
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Publication number: 20090236738Abstract: A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: STATS ChipPAC, Ltd.Inventors: SeongBo Shim, KyungOe Kim, YongHee Kang
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Patent number: RE44562Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: July 26, 2012Date of Patent: October 29, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: RE44608Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: February 1, 2013Date of Patent: November 26, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: RE44761Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: February 1, 2013Date of Patent: February 11, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang