Abstract: A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch.

Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

Abstract: An implantable medical electrical lead includes an electrode assembly in which an electrical junction between a first conductor and an inner surface of a first electrode of the assembly is wedged within a first channel of at least one core member of the assembly, around which the first electrode extends. The at least one core member is formed from an insulating material, and the first channel may be one of a plurality of longitudinally extending channels arrayed around a circumference of a central lumen of the assembly, which is defined by the at least one core member. The first conductor extends along a length of the assembly, for example, defined between the first electrode and a second electrode thereof, in a helical path that travels around the central lumen.

Abstract: An external catheter stabilizer device includes a base portion that attaches at a patient, a retaining element that retains a catheter tube, and a pivot element that pivotally attaches the retaining element to the base portion. The pivot element includes a shaft and a larger diameter head at an end of the shaft. The housing includes a key hole having a wider portion and a narrower portion. The housing is positioned at the base portion by receiving the head of the pivot element through the wider portion of the key hole and moving the shaft of the pivot element along the key hole to position the shaft of the pivot element at the narrower portion of the key hole. With the pivot element positioned at the narrower portion of the key hole, the housing maintains the pivot element at the narrower portion when the housing is closed.

Abstract: Systems and methods are disclosed for communicating via a communications network with a load control system of a respective user environment, receiving information on the load control system via the communications network, displaying graphical user interfaces based on the received information, and controlling and configuring the load control system via graphical user interfaces by communicating via the communications network messages with the load control system.

Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

Abstract: A compression garment may be used for measuring fluid buildup in a subcutaneous tissue space. The compression garment may include a processor, an emitter, and a detector. The emitter and the detector are coupled to the processor. The emitter may be configured to emit a signal into a subcutaneous tissue space of a subject. The signal may be reflected by the subcutaneous tissue space. The detector may be configured to receive the reflected signal. The processor may be configured to determine a fluid status in the subcutaneous tissue space. The fluid buildup in the subcutaneous tissue space may be based on an energy level of the reflected signal.

Abstract: A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 ?m-20 ?m.

Abstract: An exercise storage system includes a storage compartment including at least one storage element. Exercise equipment is stored on the storage elements. A door is connected to the storage compartment with a hinge such that the viewing angle of the door is adjustable. A display on the door includes a backlit display and a mirrored display. A user may select exercise equipment from the storage compartment and perform an exercise activity while viewing the display.

Abstract: A handheld fluid sprayer (10) is configured to draw spray fluid from a reservoir (14) mounted on the fluid sprayer and eject the spray fluid through a nozzle (32). The reservoir is removably mounted to the fluid sprayer. A filling apparatus can connect to the reservoir at the same interfaced that the reservoir (14) connects to the fluid sprayer (10). The filling apparatus can be used to refill the reservoir (14).

Abstract: A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch.

Abstract: An external catheter stabilizer device for stabilizing and retaining a catheter tube includes a base portion configured to adhesively attach at a patient, a retaining element configured to retain a catheter tube thereat, and a pivot element that pivotally attaches the retaining element to the base portion so as to allow for pivotal movement of the retaining element about a pivot axis generally normal to the patient where the base portion is attached. The retaining element includes a guide pin protruding therefrom and spaced from the pivot element. Pivotal movement of the retaining element relative to the base portion is limited to a selected range via engagement of the guide pin of the retaining element with an arcuate slot at the base portion.

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

Abstract: Techniques to synchronize changes in physical and virtual environments. An environmental change that will occur during a specified playback event within an interactive game is determined. An amount of time sufficient to permit an environmental device to effect a desired change in the physical environment before the specified playback event occurs is determined. The environmental device is controlled based on the amount of time, to effect the desired change synchronously with the environmental change.

Abstract: A coupler for a helical pile system is described. The coupler includes at least two sections of square tube. A first section is nested within and affixed to the second section. The first section may further include an inner width by which the first section is configured to receive two pieces of rectangular bar stocks of a helical pile system. The at least two sections each include at least two pairs of aligned through holes, for receiving first and second bolts. By the first bolt and second bolts, the two pieces of rectangular bar stock may be coupled. The first section may thus transfer torsion between the two pieces of rectangular bar stock, such as when screwing the helical pile system into the earth. The second section of square tube may further improve the torsional capacity of the coupler.

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.