Abstract: To reconstruct data transmitted over a transmission path, for example a cable, the corresponding signal received by the receiver is firstly amplified and subsequently made discrete by means of an A/D-converter (6), in order to obtain a suitable digital signal, whereby the signal amplified for this purpose is scanned with a relatively low sampling rate, which can frequently lie in the Nyquist range or can be even less than the Nyquist frequency. Subsequently the signal made discrete in this way is filtered by means of a digital high pass filter (8) and equalized by means of a digital cable approximation filter (9) to compensate any distortion occurring during the transmission over the transmission path. By means of a phase locked loop (14, 18) a regenerated clock (CLK) and synchronous with this clock the originally transmitted data (DATA) is recovered from the digital signal processed in this way.

Abstract: High-speed router for transmitting data packets, containing header data and useful data, between data networks, the router including a plurality of data processing processors for parallel data processing of the header data, a demultiplexer for separating the data packets into header data and useful data, and a distribution processor for distributing the separated header data among the data processing processors. The distribution processor distributes the header data at least in part on the basis of a priority specified by the header data and the workload of the data processing processors.

Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).

Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p?[1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q?[1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t?[1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).

Abstract: A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means (10) for the production of the signals with a certain signal form and signal adjustment means (20) for the adaptation or pre-distortion of the signals. The signal generation means (10) according to the invention are digitally realized, by using a programmable shift register (14), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (1). The signal adjustment means (20) comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters (22) with a downstream multiplexer (24).

Abstract: Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter (4); and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolatio

Abstract: A comb filter arrangement has an integrator that outputs an input value to a signal path. The signal path includes a delay stage for adjusting the input value using a delay factor, a decimator that converts the input value into a decimated output value using a non-integral factor, a differentiator that generates an intermediate output value from the input value, and an interpolation arrangement that receives the intermediate output value and generates a decimated sequence of the output value.

Abstract: The invention relates to a device for correcting a receiver signal which is associated with an emission signal transmitted in a distorted transmission system. The emission signal comprises periods which can be determined by analyzing the received signal wherein determined properties are exhibited which are suitable for adjusting the correction. According to one embodiment, the device comprises a component for adjusting the correction based upon an analysis of the received signal and a component for monitoring and enabling the adjusting component when the received signal associated with the transmission signal exhibits certain characteristics.

Abstract: A method and a device for reconstructing data, clocked at a symbol rate, from a signal which has been distorted by transmission of a transmission link, are disclosed. The method or respectively, the device, being predominantly performed or implemented, respectively, by means of digital circuit technology in order to improve the quality of the data recovery. The method comprises amplifying the signal amplitude attenuated by the transmission; filtering high-frequency interference frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter (3); performing a cable approximation by means of a digitally implemented cable approximation filter (7) in order to obtain an equalized signal; and recovering the data from the equalized signal by means of a phase-locked loop (20).

Abstract: The invention relates to a circuit configuration for two-wire/four-wire conversion. The circuit configuration has a receiver which is coupled on an input side to a digital two-wire reception path via which its receives a digital signal. A signal-processor is connected downstream of the receiver and emits a first and second signal. An echo-canceling device receives the first signal and emits a third signal. A digital-to-analog converter is provided which receives the second signal and emits a fourth signal. A hybrid circuit is coupled to an analog four-wire transmission-reception path, receives the fourth signal, and emits a fifth signal. An analog-to-digital converter receives the fifth signal and emits a sixth signal. A transmitter receives the sixth signal and is coupled on an output side to a digital two-wire transmission path and emits a digital transmitted signal to the latter. In the invention, the digital-to-analog converter has a sigma-delta modulator.

Abstract: An arrangement to analyze the nonlinear properties of a communication channel that uses a test signal having a number of tones. The test signal is transmitted via the communication channel to be evaluated. For the individual tones of the test signal, equidistant tone frequencies are selected, some of these tone frequencies not being used for the test signal. By the use of frequency shifters in the form of digital modulators, which shift the frequency spectrum of the transmitted test signal to zero by in each case one tone frequency value that is not used, nonlinear interference can be determined with the aid of a low-pass filter.

Abstract: To reconstruct data transmitted over a transmission path, for example a cable, the corresponding signal received by the receiver is firstly amplified and subsequently made discrete by means of an A/D-converter (6), in order to obtain a suitable digital signal, whereby the signal amplified for this purpose is scanned with a relatively low sampling rate, which can frequently lie in the Nyquist range or can be even less than the Nyquist frequency. Subsequently the signal made discrete in this way is filtered by means of a digital high pass filter (8) and equalized by means of a digital cable approximation filter (9) to compensate any distortion occurring during the transmission over the transmission path. By means of a phase locked loop (14, 18) a regenerated clock (CLK) and synchronous with this clock the originally transmitted data (DATA) is recovered from the digital signal processed in this way.

Abstract: An arrangement to analyze the nonlinear properties of a communication channel that uses a test signal having a number of tones. The test signal is transmitted via the communication channel to be evaluated. For the individual tones of the test signal, equidistant tone frequencies are selected, some of these tone frequencies not being used for the test signal. By the use of frequency shifters in the form of digital modulators, which shift the frequency spectrum of the transmitted test signal to zero by in each case one tone frequency value that is not used, nonlinear interference can be determined with the aid of a low-pass filter.

Abstract: High-speed router for transmitting data packets, containing header data and useful data, between data networks, the router (1) having a plurality of data processing processors (12, 13, 14, 15) for parallel data processing of the header data.

Abstract: Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolation filt

Abstract: An adaptive network includes a summation node for receiving an input signal and delivering an output signal. A decision unit receives the output signal of the summation node as an input signal and has an output for delivering an output signal being a differential signal between the input and output signals of the decision unit. An adaptive feedback branch receives the output signal of the decision unit and has status variables, coefficients and an output. A changeover switch unit couples the output of the feedback branch to the summation node. A monitoring unit monitors an error magnitude of the output signal of the decision unit. The monitoring unit triggers the changeover switch unit in the next clock cycle if a first signal value having an amplitude exceeding a certain threshold value appears, for causing the summation node to be acted upon by a digital zero signal, for setting the status variables of the feedback branch to zero and for freezing the coefficients of the feedback branch.

Abstract: A method and a circuit configuration for filtering a digital value with improved noise behavior include adding a digital input value and a feedback value to form a digital output value. The feedback value is equal to a first variable from which a second variable is subtracted, from which the second variable shifted m places to the right is subtracted, and to which the first variable is added. The first variable is equal to a bottom m bits of a previous digital output value and always represents a positive value. The second variable is equal to a previous first variable from which a previous second variable shifted arithmetically by m bits to the right is subtracted. The feedback value is calculated with at least one additional least significant bit until at least a last addition with the first variable. Subsequently, an expansion is no longer taken into account.

Abstract: A method for generating a digital sine wave signal having a predetermined sampling rate includes generating a pulse train with an alternating or constant amplitude sign, at a sampling frequency having a predetermined sampling rate frequency divided by 2.sup.n. An envelope curve is generated. The sampling rate is doubled. The doubling of the sampling rate is repeated until generation of a desired sine wave signal in an unfiltered spectrum of the generated signal. Undesired frequency components are filtered out. The sampling rate is optionally re-increased by oversampling a previously generated signal. A circuit configuration for carrying out the method includes a unit for generating digital sampling values. A filter for generating an envelope curve is connected downstream of the unit for generating digital sampling values. Units for raising a sampling frequency are connected downstream of the filter for generating an envelope curve. A digital filter filters the generated digital sampling values.

Abstract: An adaptive nonrecursive digital filter includes a first filter unit having N controllable filter coefficients. A control unit controls the filter coefficients as a function of an input signal applied to the first filter unit at a given sampling rate and as a function of a difference between a reference signal and an output signal output by the first filter unit, in accordance with the least mean error square in each case. The first filter unit and the control unit sample the input signal and the reference signal continuously, with a cyclically varying delay, at a correspondingly increased sampling rate. A second filter unit is operated at the given sampling rate and has N controllable filter coefficients. The second filter unit receives the input signal, outputs a further output signal and has filter coefficients also being controlled by the control unit.

Abstract: An integratable circuit configuration includes an analog signal network being subject to fluctuations in a given way. A switched capacitor network is connected in series with the analog signal network and receives settable coefficients. An analog comparison network which is subject to the fluctuations in the given way, receives an excitation signal and supplies a response signal in response to the excitation signal. An evaluation circuit is connected to the analog comparison network and to the switched capacitor network for comparing the response signal with a reference signal and setting the coefficients of the switched capacitor network as a function of the comparison.