Abstract: An integratable circuit configuration includes an analog signal network being subject to fluctuations in a given way. An analog/digital converter is connected downstream of the analog signal network. A digital signal network is connected downstream of the analog/digital converter for receiving settable coefficients. An analog comparison network being subject to the fluctuations in the same given way receives an excitation signal and supplies a response signal in response to the excitation signal. An evaluation circuit is connected to the analog comparison network and to the digital signal network for comparing the response signal with a reference signal and setting the coefficients of the digital signal network as a function of the comparison. According to another embodiment, a digital/analog converter is connected upstream of the analog signal network. Then the digital signal network is connected upstream of the digital/analog converter.

Abstract: A method and network configuration attain a continuous variation in the transfer function of an adaptive recursive network having multi-port subnetworks associated with parameters of the network, for processing discrete-time signals upon continuous variations in the parameters. The multi-port subnetworks are represented by elementary subnetworks being isolated with respect to the parameters. Each elementary subnetwork has parameters which can assume values in a given total value range being represented by a differently structured elementary subrange network being associated with adjacent value ranges of the respective parameter and having a transfer function varying continuously upon continuous variations in the parameter. A switchable inverter and elementary subnetworks having parameters which can only assume values in a range of the given total value range, are optionally represented by a combined subnetwork.

Abstract: In an adaptive balance filter, the coefficients of an adaptive filter are only taken over in a shadow filter, when a digital input signal to be transmitted is recognized as a wide band signal.

Abstract: A circuit configuration for digital bit-serial signal processing includes n input shift registers each being written in parallel or serially with an input data word and then read out by shifting to the right. Sign repetition devices are each assigned to a respective one of the input shift registers for continuously generating and shifting an algebraic sign of the input data word onward in the shift to the right. A serial arithmetic unit is connected downstream of the input shift registers for serially outputting output data words. m output shift registers connected downstream of the serial arithmetic unit are written in serially with the output data words and read out in parallel and/or serially. A control unit is connected to the serial arithmetic unit.

Abstract: A communication system has a two-wire communications path carrying analog transmission and reception signals, and a four-wire communications path including a two-wire transmission path carrying digital transmission signals and a two-wire reception path carrying digital reception signals. A two-wire/four-wire converter for coupling the two-wire communications path to the four-wire communications path includes an analog/digital converter having an input coupled to the two-wire communications path and an output. A digital filter has an adjustable communications function for generating a predetermined terminating impedance for the two-wire transmission path. The digital filter has an input connected to the output of the analog/digital converter and an output connected to the two-wire reception path. An adder has one input connected to the two-wire reception path, another input connected to the two-wire transmission path and an output.

Abstract: A two-wire/four-wire converter for coupling a two-wire communications path carrying analog transmission and reception signals to a four-wire communications path having a two-wire transmission path carrying digital transmission signals and a two-wire reception path carrying digital reception signals, includes an analog/digital converter having an input coupled to the two-wire communications path and an output coupled to the two-wire reception path. An adder has one input connected to the two-wire reception path and another input connected to the two-wire transmission path. A digital filter with an adjustable communications function generates a predetermined terminating impedance for the two-wire transmission path. The digital filter has an input connected to the output of the adder and an output. A subtractor has one input connected to the output of the digital filter, another input coupled to the output of the analog/digital converter and an output.

Abstract: An adaptive, recursive digital wave filter includes a transfer filter and a gradient filter each having a respective adaptor with a given coefficient. A method and circuit configuration for avoiding overflows in the filter include multiplying a signal emitted by the transfer filter to the gradient filter by a scaling factor being equal to the difference between 1 and the amount of the given coefficient.

Abstract: In a method and configuration for improving the dynamic range of an adaptive recursive network for processing discrete-time signals, gradient signals are formed from output signals of the network with respect to network parameters. The output signals of the network are compared with set-point signals to form differential signals. Signals of a signum function of the gradient signals are formed. The signals of the signum function are multiplied with the differential signals to form correction signals proportional to the product of the signals of the signum function and the differential signals.

Abstract: An analog/digital converter configuration includes sigma-delta modulators being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate. The sigma-delta modulators have input circuits with amplification factors. Amplifiers are each connected upstream of a respective one of the sigma-delta modulators. First sampling rate reducers are each connected downstream of a respective one of the sigma-delta modulators. Damping elements are each connected downstream of a respective one of the first sampling rate reducers. Each of the damping elements have a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a corresponding one of the sigma-delta modulators. A priority logic is connected downstream of the damping elements. A second sampling rate reducer is connected downstream of the priority logic. An output is connected downstream of the second sampling rate reducer.

Abstract: A digital circuit for sampling rate variation and signal filtering includes an input, an output, a lattice wave digital filter having a plurality of filter branches connected to the input, the filter branches each having at least two series-connected filter subgroups with basic filter elements each formed of one two port adaptor made up of adders and multipliers and one time-lag device, a device disposed between the at least two filter subgroups for varying the sampling rate and for generating a phase change in a digital system, and an adder connected between filter branches and the output. A method for constructing the circuit is also provided.

Abstract: A method and apparatus for preparing samples of a time-dependent signal (Se) in a data processing system which comprises an arithmetic unity (1), a control unit (2), a memory (3) and an address modification unit (13) wherein with a stored dataset of individual samples, for updating these step-by-step during every successive sampling period and respectively reading out the dated dataset and supplying it to the arithmetic unit (1), is achieved such that an address sequence which traverses a prescribed memory area is output via the address modification unit (13), so that a sequence of samples is written. Subsequently, the memory area is cyclically traversed with a plurality of address strings, whereby the stored samples are successively read out onto a bus line (4) and, when reaching an individual memory location within each of the address strings, the oldest sample stored there is overwritten by a further sample. The method is distinguished by a minimum of re-storing operations.