Patents by Inventor Lakshminarayan Viswanathan

Lakshminarayan Viswanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269678
    Abstract: Microelectronic systems having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the step or process of obtaining a microelectronic component from which a heat dissipation post projects. The microelectronic component is placed or seated on a substrate, such as a multilayer printed circuit board, having a socket cavity therein. The heat dissipation post is received in the socket cavity as the microelectronic component is seated on the substrate. Concurrent with or after seating the microelectronic component, the microelectronic component and the heat dissipation post are bonded to the substrate. In certain embodiments, the heat dissipation post may be dimensioned or sized such that, when the microelectronic component is seated on the substrate, the heat dissipation post occupies a volumetric majority of the socket cavity.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Mahesh K. Shah, Lu Li, David Abdo, Geoffrey Tucker, Carl Emil D'Acosta, Jaynal A. Molla, Justin Eugene Poarch, Paul Hart
  • Publication number: 20190109060
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Publication number: 20190098743
    Abstract: High thermal performance microelectronic modules containing sinter-bonded heat dissipation structures are provided, as are methods for the fabrication thereof. In various embodiments, the method includes the steps or processes of providing a module substrate, such as a circuit board, including a cavity having metallized sidewalls. A sinter-bonded heat dissipation structure is formed within the cavity. The sintered-bonded heat dissipation structure is formed, at least in part, by inserting a prefabricated thermally-conductive body, such as a metallic (e.g., copper) coin into the cavity. A sinter precursor material (e.g., a metal particle-containing paste) is dispensed or otherwise applied into the cavity and onto surfaces of the prefabricated thermally-conductive body before, after, or concurrent with insertion of the prefabricated thermally-conductive body.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Applicant: NXP USA, INC.
    Inventors: JAYNAL A. MOLLA, LAKSHMINARAYAN VISWANATHAN, ELIE A. MAALOUF, GEOFFREY TUCKER
  • Patent number: 10211177
    Abstract: A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Scott M. Hayes, Scott D. Marshall, Mahesh K. Shah
  • Publication number: 20190051571
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Publication number: 20190043774
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Publication number: 20190043775
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Patent number: 10199302
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10199303
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Publication number: 20190021162
    Abstract: Methods for producing high thermal performance microelectronic modules containing sinter-bonded heat dissipation structures. In one embodiment, the method includes embedding a sinter-bonded heat dissipation structure in a module substrate. The step of embedding may entail applying a sinter precursor material containing metal particles into a cavity provided in the module substrate, and subsequently sintering the sinter precursor material at a maximum processing temperature less than a melt point of the metal particles to produce a sintered metal body bonded to the module substrate. A microelectronic device and a heatsink are then attached to the module substrate before, after, or concurrent with sintering such that the heatsink is thermally coupled to the microelectronic device through the sinter-bonded heat dissipation structure. In certain embodiments, the microelectronic device may be bonded to the module substrate at a location overlying the thermally-conductive structure.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Applicant: NXP USA, INC.
    Inventors: LAKSHMINARAYAN VISWANATHAN, ELIE A. MAALOUF, GEOFFREY TUCKER
  • Publication number: 20190013242
    Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 10, 2019
    Inventors: Jaynal A. Molla, Lakshminarayan Viswanathan, David Abdo, Colby Greg Rampley, Fernando A. Santos
  • Patent number: 10147698
    Abstract: A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 4, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Michael Watts
  • Patent number: 10141182
    Abstract: Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 27, 2018
    Assignee: NXP USA, INC.
    Inventors: Jaynal A. Molla, Lakshminarayan Viswanathan, Geoffrey Tucker
  • Publication number: 20180317312
    Abstract: A packaged microelectronic component includes a substrate and a semiconductor die coupled to a top surface of the substrate. A method of attaching the packaged microelectronic component to a secondary structure entails applying a metal particle-containing material to at least one of a bottom surface of the substrate and a mounting surface of the secondary structure. The packaged microelectronic component and the secondary structure are arranged in a stacked relationship with the metal particle-containing material disposed between the bottom surface and the mounting surface. A low temperature sintering process is performed at a maximum process temperature less than a melt point of the metal particles to transform the metal particle-containing material into a sintered bond layer joining the packaged microelectronic component and the secondary structure. In an embodiment, the substrate may be a heat sink for the packaged microelectronic component and the secondary structure may be a printed circuit board.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 1, 2018
    Inventors: Lakshminarayan Viswanathan, Lu Li, Mahesh K. Shah, Paul Richard Hart
  • Patent number: 10109594
    Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 23, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Michael E. Watts, David F. Abdo
  • Patent number: 10104759
    Abstract: Methods for producing high thermal performance microelectronic modules containing sinter-bonded heat dissipation structures. In one embodiment, the method includes embedding a sinter-bonded heat dissipation structure in a module substrate. The step of embedding may entail applying a sinter precursor material containing metal particles into a cavity provided in the module substrate, and subsequently sintering the sinter precursor material at a maximum processing temperature less than a melt point of the metal particles to produce a sintered metal body bonded to the module substrate. A microelectronic device and a heatsink are then attached to the module substrate before, after, or concurrent with sintering such that the heatsink is thermally coupled to the microelectronic device through the sinter-bonded heat dissipation structure. In certain embodiments, the microelectronic device may be bonded to the module substrate at a location overlying the thermally-conductive structure.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: October 16, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Elie A. Maalouf, Geoffrey Tucker
  • Publication number: 20180270960
    Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 20, 2018
    Inventors: Lakshminarayan VISWANATHAN, Audel A. SANCHEZ, Fernando A. SANTOS, Jerry L. WHITE
  • Patent number: 10074588
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 11, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
  • Publication number: 20180153030
    Abstract: Methods for producing high thermal performance microelectronic modules containing sinter-bonded heat dissipation structures. In one embodiment, the method includes embedding a sinter-bonded heat dissipation structure in a module substrate. The step of embedding may entail applying a sinter precursor material containing metal particles into a cavity provided in the module substrate, and subsequently sintering the sinter precursor material at a maximum processing temperature less than a melt point of the metal particles to produce a sintered metal body bonded to the module substrate. A microelectronic device and a heatsink are then attached to the module substrate before, after, or concurrent with sintering such that the heatsink is thermally coupled to the microelectronic device through the sinter-bonded heat dissipation structure. In certain embodiments, the microelectronic device may be bonded to the module substrate at a location overlying the thermally-conductive structure.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Applicant: NXP USA, INC.
    Inventors: LAKSHMINARAYAN VISWANATHAN, ELIE A. MAALOUF, GEOFFREY TUCKER
  • Patent number: 9984951
    Abstract: Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. The first metal layer and the metal particle-containing layer are then arranged in a stacked relationship with a second metal layer such that the precursor layer is disposed between the first and second metal layers. A low temperature sintering process is then carried-out at a maximum process temperature less than a melt point of the metal particles to transform the precursor layer into a sintered bond layer joining the first and second metal layers in a sintered multilayer heat sink. In embodiments wherein the sintered multilayer heat sink is contained within a heat sink panel, singulation may be carried-out to separate the sintered multilayer heat sink from the other heat sinks within the panel.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 29, 2018
    Assignee: NXP USA, INC.
    Inventor: Lakshminarayan Viswanathan