Patents by Inventor Lakshminarayan Viswanathan

Lakshminarayan Viswanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240213114
    Abstract: A substrate is bonded to a conductive metallic flange via a free-standing heterostructure thermal interface material that includes physically distinct volumes of different conductive materials. The heterostructure thermal interface material (a bimetallic foil, for example) is metallurgically bonded to the bottom of the substrate on one side and metallurgically bonded to the flange on an opposite side. The constituent materials forming the thermal interface material and their dimensions can be chosen to achieve a desired thermal and/or electrical conductivity while allowing the coefficient of thermal expansion (CTE) to be matched to the substrate and/or the flange.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Inventors: Sharan Kishore, Lu Li, Jaynal A. Molla, Fui Yee Lim, Freek Egbert van Straten, Lakshminarayan Viswanathan
  • Patent number: 12014971
    Abstract: A thermal interface structure for transferring heat from an electronic component to a system heat sink includes a stack of one or more layers of a stiff thermal interface material and one or more layers of a compliant thermal interface material stacked on and connected to the one or more layers of the compliant thermal interface material. In some embodiments, the thermal interface structure also may include one or more layers of a shape memory alloy and/or a collapsible encasement.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: June 18, 2024
    Assignee: NXP USA, Inc.
    Inventors: Lu Li, Sharan Kishore, Freek Egbert van Straten, Lakshminarayan Viswanathan
  • Patent number: 12015004
    Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: June 18, 2024
    Assignee: NXP USA, Inc.
    Inventors: Li Li, Lakshminarayan Viswanathan, Jeffrey Kevin Jones
  • Patent number: 11990872
    Abstract: Power amplifier modules (PAMs) having topside cooling interfaces are disclosed, as are methods for fabricating such PAMs. In embodiments, the method includes attaching the RF power die to a die support-surface of a module substrate. The RF power die is attached to the module substrate in an inverted orientation such that a frontside of the RF power die faces the module substrate. When attaching the RF power die to the module substrate, a frontside input/output interface of the RF power die is electrically coupled to corresponding substrate interconnect features of the module substrate. The method further includes providing a primary heat extraction path extending from the transistor channel of the RF power die to a topside cooling interface of the PAM in a direction opposite the module substrate.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 21, 2024
    Assignee: NXP USA, Inc.
    Inventors: Geoffrey Tucker, Lakshminarayan Viswanathan, Jeffrey Kevin Jones, Elie A. Maalouf
  • Patent number: 11984429
    Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: May 14, 2024
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Scott Duncan Marshall, Lakshminarayan Viswanathan, Taek Kyu Kim, Ricardo Uscola, Fernando A. Santos
  • Patent number: 11929310
    Abstract: Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: March 12, 2024
    Assignee: NXP USA, Inc.
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Patent number: 11830842
    Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 28, 2023
    Assignee: NXP USA., Inc.
    Inventors: Li Li, Lakshminarayan Viswanathan, Jeffrey Kevin Jones
  • Publication number: 20230369272
    Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Li Li, Lakshminarayan Viswanathan, Jeffrey Kevin Jones
  • Publication number: 20230291369
    Abstract: Power amplifier systems including field trapper structures are disclosed. In embodiments, the power amplifier system includes a printed circuit board (PCB), a power amplifier module (PAM), and a field trapper structure. The PAM includes, in turn, a topside radio frequency (RF) input terminal, topside RF output terminal, a PAM topside surface on which the topside RF input terminal and the topside RF output terminal are located. The PAM is mounted to the PCB in an inverted orientation such that the PAM topside surface is positioned adjacent and faces a module mount region provided on a frontside of the PCB. The field trapper structure includes a first field trapper patch, which extends parallel to the PCB frontside, is composed of an electrically-conductive material, and is located within or adjacent the module mount region in the thickness direction.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 14, 2023
    Inventors: Kevin Kim, Vikas Shilimkar, Lakshminarayan Viswanathan
  • Patent number: 11749639
    Abstract: Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: September 5, 2023
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Publication number: 20230230924
    Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.
    Type: Application
    Filed: February 28, 2023
    Publication date: July 20, 2023
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Publication number: 20230197645
    Abstract: Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Inventors: Zhiwei Gong, LI Li, Lu Li, Lakshminarayan Viswanathan, Fernando A. Santos, Burton Jesse Carpenter
  • Publication number: 20230187325
    Abstract: Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Publication number: 20230133034
    Abstract: A device includes a package body including a central flange and an amplifier module mounted to the central flange of the surface-mount device. The amplifier module includes a module substrate mounted to the central flange. The module substrate includes a first die mount window, a first circuitry on a first surface of the module substrate, a second circuitry on the first surface of the module substrate, and a first amplifier die mounted on the central flange. The first amplifier die is at least partially disposed within the first die mount window and the first amplifier die is electrically connected to the first circuitry and the second circuitry. The first circuitry is electrically connected to a first lead of the package body and the second circuitry is electrically connected to a second lead of the package body.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 4, 2023
    Inventors: Lu LI, Li LI, Lakshminarayan VISWANATHAN, Zhiwei GONG, Fernado A. SANTOS, Elie A. Maalouf, Eduard Jan PABST
  • Publication number: 20230111320
    Abstract: Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.
    Type: Application
    Filed: October 13, 2021
    Publication date: April 13, 2023
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Publication number: 20230115340
    Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 13, 2023
    Inventors: Yun Wei, Scott Duncan Marshall, Lakshminarayan Viswanathan, Taek Kyu Kim, Ricardo Uscola, Fernando A. Santos
  • Patent number: 11621228
    Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Lu Li, Lakshminarayan Viswanathan, Freek Egbert van Straten
  • Patent number: 11621673
    Abstract: Embodiments of Doherty Power Amplifier (PA) and other PA packages are provided, as are systems including PA packages. In embodiments, the PA package includes a package body having a longitudinal axis, a first group of input-side leads projecting from a first side of the package body and having an intra-group lead spacing, and a first group of output-side leads projecting from a second side of the package body and also having the intra-group lead spacing. A first carrier input lead projects from the first package body side and is spaced from the first group of input-side leads by an input-side isolation gap, which has a width exceeding the intra-group lead spacing. Similarly, a first carrier output lead projects from the second package body side, is laterally aligned with the first carrier input lead, and is separated from the first group of output-side leads by an output-side isolation gap.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Jean-Christophe Nanan, David James Dougherty, Scott Duncan Marshall, Lakshminarayan Viswanathan, Xavier Hue
  • Patent number: 11621231
    Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
  • Publication number: 20220384307
    Abstract: A thermal interface structure for transferring heat from an electronic component to a system heat sink includes a stack of one or more layers of a stiff thermal interface material and one or more layers of a compliant thermal interface material stacked on and connected to the one or more layers of the compliant thermal interface material. In some embodiments, the thermal interface structure also may include one or more layers of a shape memory alloy and/or a collapsible encasement.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: Lu Li, Sharan Kishore, Freek Egbert van Straten, Lakshminarayan Viswanathan