Abstract: Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.

Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

Abstract: Power amplifier systems including field trapper structures are disclosed. In embodiments, the power amplifier system includes a printed circuit board (PCB), a power amplifier module (PAM), and a field trapper structure. The PAM includes, in turn, a topside radio frequency (RF) input terminal, topside RF output terminal, a PAM topside surface on which the topside RF input terminal and the topside RF output terminal are located. The PAM is mounted to the PCB in an inverted orientation such that the PAM topside surface is positioned adjacent and faces a module mount region provided on a frontside of the PCB. The field trapper structure includes a first field trapper patch, which extends parallel to the PCB frontside, is composed of an electrically-conductive material, and is located within or adjacent the module mount region in the thickness direction.

Abstract: Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

Abstract: Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.

Abstract: Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.

Abstract: A device includes a package body including a central flange and an amplifier module mounted to the central flange of the surface-mount device. The amplifier module includes a module substrate mounted to the central flange. The module substrate includes a first die mount window, a first circuitry on a first surface of the module substrate, a second circuitry on the first surface of the module substrate, and a first amplifier die mounted on the central flange. The first amplifier die is at least partially disposed within the first die mount window and the first amplifier die is electrically connected to the first circuitry and the second circuitry. The first circuitry is electrically connected to a first lead of the package body and the second circuitry is electrically connected to a second lead of the package body.

Abstract: Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.

Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

Abstract: Embodiments of Doherty Power Amplifier (PA) and other PA packages are provided, as are systems including PA packages. In embodiments, the PA package includes a package body having a longitudinal axis, a first group of input-side leads projecting from a first side of the package body and having an intra-group lead spacing, and a first group of output-side leads projecting from a second side of the package body and also having the intra-group lead spacing. A first carrier input lead projects from the first package body side and is spaced from the first group of input-side leads by an input-side isolation gap, which has a width exceeding the intra-group lead spacing. Similarly, a first carrier output lead projects from the second package body side, is laterally aligned with the first carrier input lead, and is separated from the first group of output-side leads by an output-side isolation gap.

Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.

Abstract: A thermal interface structure for transferring heat from an electronic component to a system heat sink includes a stack of one or more layers of a stiff thermal interface material and one or more layers of a compliant thermal interface material stacked on and connected to the one or more layers of the compliant thermal interface material. In some embodiments, the thermal interface structure also may include one or more layers of a shape memory alloy and/or a collapsible encasement.

Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.

Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.

Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.

Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.