Patents by Inventor Lan Chang

Lan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367193
    Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui, Yung-Cheng Lu
  • Patent number: 11495464
    Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui, Yung-Cheng Lu
  • Patent number: 11467400
    Abstract: An information display method and an information display system are provided. The method is adapted to the information display system including a first image capturing device and a transparent display, and the method includes the following steps. A pattern image is obtained by shooting a pattern placed on a real object through the first image capturing device, wherein the real object is located on one side of the transparent display. Relative position information between the transparent display and the pattern is obtained according to the pattern image. Augmented image data is obtained according to the relative position information. The augmented image data is displayed through the transparent display, wherein the augmented image data include a virtual object augmented based on the real object.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: October 11, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Ruo-Lan Chang, Pi-Hsien Wang, Chih-Chia Chang, Yu-Hsin Lin
  • Patent number: 11359425
    Abstract: A dual-shaft hinge with alternative rotation includes: a pivotal base, and having an axial swinging member and a radial moving member; a first core shaft, having a first shaft rod, a first guiding slot and a first latching slot, and the first core shaft is formed in an unlocked status when the first latching slot is engaged with the radial moving member; and a second core shaft, having a second shaft rod, a second guiding slot and at least one second latching slot; the second core shaft is formed in a locked status when the at least one second latching slot is engaged with the radial moving member, and the first core shaft is in the unlocked status, thereby enabling the first core shaft and the second core shaft to alternatively rotate.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: June 14, 2022
    Assignee: JARLLYTEC CO., LTD.
    Inventor: Kai-Lan Chang
  • Publication number: 20220165808
    Abstract: An electronic device includes a transparent substrate, a number of pixel structures and a first trace structure. The transparent substrate includes a transparent region and a trace region. Each of the pixel structures has a sub-pixel structure of first color and a sub-pixel structure of second color. The sub-pixel structure of first color has a light emitting element of first color. The sub-pixel structure of second color has a light emitting element of second color. The first trace structure includes a first main trace, a first auxiliary trace and a second auxiliary trace. The first main trace is disposed in the trace region and surrounds a portion of the transparent region. The first auxiliary trace and the second auxiliary trace are electrically connected to the first main trace, and are electrically connected to the corresponding sub-pixel structure of first color and the corresponding sub-pixel structure of second color, respectively.
    Type: Application
    Filed: November 27, 2020
    Publication date: May 26, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ying-Ting LIOU, Ruo-Lan CHANG, Wen-Yu KUO, Wen-Ya CHAO, Wei-Chung CHEN
  • Publication number: 20220020865
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: March 10, 2021
    Publication date: January 20, 2022
    Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
  • Publication number: 20220013364
    Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 13, 2022
    Inventors: Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui, Yung-Cheng Lu
  • Publication number: 20210407925
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Application
    Filed: November 17, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei CHANG, Chien-Shun LIAO, Sung-Li WANG, Shuen-Shin LIANG, Shu-Lan CHANG, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG
  • Publication number: 20210343897
    Abstract: A light-emitting diode (LED) structure includes an active region that has at least one aluminum-containing quantum well (QW) stack that emits light from the LED structure when activated. The LED structure exhibits a modified internal quantum efficiency value, which is higher than a LED structure that does not include aluminum within a QW stack. The LED structure also exhibits a modified peak wavelength, which is longer than an unmodified peak wavelength of the unmodified LED structure.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 4, 2021
    Inventors: Ying-Lan CHANG, Benjamin LEUNG, Miao-Chan TSAI, Richard Peter SCHNEIDER, Sheila HURTT, Gang HE
  • Publication number: 20210292370
    Abstract: Human anti-AAV capsid polyclonal antibody conformational epitopes including those of neutralizing antibodies are provided. The epitopes can be recognized by human anti-AAV2 or other AAV strain-derived capsid polyclonal antibodies. One or more of the epitopes may be mutated to form AAV2 and other AAV strain-derived capsids that can escape antibody neutralization. Methods of identifying human anti-AAV capsid polyclonal antibody conformational epitopes are also provided.
    Type: Application
    Filed: November 4, 2020
    Publication date: September 23, 2021
    Inventors: Kei Adachi, Xiao Lan Chang, Hiroyuki Nakai
  • Publication number: 20210257523
    Abstract: An emitting device comprising a first light emitter adapted to emit a first radiation, and a second light emitter adapted to emit a second radiation different from the first radiation, the first light emitter comprising a first semiconducting structure and a first radiation converter, the second light emitter comprising a second semiconducting structure and a second radiation converter, each semiconducting structure comprising a semiconducting layer adapted to emit a third radiation, each radiation converter comprising a set of particles able to convert the third radiation into the first or second radiation, the particles of the first radiation converter being attached to a surface by a bulk of photosensitive resin and the particles of the second radiation converter being attached to a surface by grafting.
    Type: Application
    Filed: June 27, 2019
    Publication date: August 19, 2021
    Inventors: Ying-Lan CHANG, Sylvia SCARINGELLA, Ivan-Christophe ROBIN, Abdelhay ABOULAICH
  • Publication number: 20210172225
    Abstract: A dual-shaft hinge with alternative rotation includes: a pivotal base, and having an axial swinging member and a radial moving member; a first core shaft, having a first shaft rod, a first guiding slot and a first latching slot, and the first core shaft is formed in an unlocked status when the first latching slot is engaged with the radial moving member; and a second core shaft, having a second shaft rod, a second guiding slot and at least one second latching slot; the second core shaft is formed in a locked status when the at least one second latching slot is engaged with the radial moving member, and the first core shaft is in the unlocked status, thereby enabling the first core shaft and the second core shaft to alternatively rotate.
    Type: Application
    Filed: June 4, 2020
    Publication date: June 10, 2021
    Inventor: Kai-Lan CHANG
  • Publication number: 20210126049
    Abstract: An emitting device comprising a first light emitter adapted to emit a first radiation and comprising at least one first semiconducting structure comprising a first semiconducting layer adapted to emit the first radiation, a second light emitter adapted to emit a second radiation different from the first radiation, the second light emitter comprising at least one second semiconducting structure comprising a second semiconducting layer adapted to emit the second radiation, and a third light emitter adapted to emit a third radiation different from the second and first radiations, the third light emitter comprising at least one third semiconducting layer adapted to emit a fourth radiation different from the third radiation, the third light emitter further comprising a radiation converter configured to convert the fourth radiation into the third radiation.
    Type: Application
    Filed: June 28, 2019
    Publication date: April 29, 2021
    Applicant: Aledia
    Inventors: Ying-Lan CHANG, Sylvia SCARINGELLA, Ivan-Christophe ROBIN, Abdelhay ABOULAICH
  • Patent number: 10987658
    Abstract: A three-way catalyst article, and its use in an exhaust system for internal combustion engines, is disclosed. The catalyst article for treating exhaust gas comprising: a substrate; and a single catalyst layer deposited directly on the substrate; wherein the single catalyst layer comprises a first platinum group metal (PGM) component, an oxygen storage component (OSC) material, and an inorganic oxide; and wherein the single catalyst layer has a total washcoat loading of less than 2.4 g/in3.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 27, 2021
    Assignee: Johnson Matthey Public Limited Company
    Inventors: Kenneth Camm, Hsiao-Lan Chang, Hai-Ying Chen, Michael Hales, Kwangmo Koo
  • Patent number: 10991649
    Abstract: A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
  • Publication number: 20210103143
    Abstract: An information display method and an information display system are provided. The method is adapted to the information display system including a first image capturing device and a transparent display, and the method includes the following steps. A pattern image is obtained by shooting a pattern placed on a real object through the first image capturing device, wherein the real object is located on one side of the transparent display. Relative position information between the transparent display and the pattern is obtained according to the pattern image. Augmented image data is obtained according to the relative position information. The augmented image data is displayed through the transparent display, wherein the augmented image data include a virtual object augmented based on the real object.
    Type: Application
    Filed: January 9, 2020
    Publication date: April 8, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Ruo-Lan Chang, Pi-Hsien Wang, Chih-Chia Chang, Yu-Hsin Lin
  • Publication number: 20210013338
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20200343357
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 29, 2020
    Inventors: Po-Chi Wu, Chia-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10790394
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10714587
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao