Abstract: Semiconductor device having first and second main electrodes with gate electrode layer inbetween, semiconductor layer stack between and in electrical contact with the first and second main electrodes having differently doped semiconductor layers. At least two semiconductor layers differ in their conductivity type and/or their doping concentration. Pillar-shaped or fin-shaped regions run through the gate electrode layer, each having a contact layer arranged at the first main electrode with a first doping concentration and a first conductivity type. Each contact layer extends to a side of the gate electrode layer facing the first main electrode, the contact layers of adjacent pillar-shaped or fin-shaped regions merge on the side of the gate electrode layer facing the first main electrode so that the contact layers of adjacent pillar-shaped or fin-shaped regions are arranged continuously on the side of the gate electrode layer facing the first main electrode.

Abstract: A power semiconductor device comprising a drift layer of a first conductivity type, at least one well region of a second conductivity type being different from the first conductivity type, and at least one first doped region of the first conductivity type and at least one second doped region of the second conductivity type, wherein the at least one well region, the at least one first doped region and the at least one second doped region are provided at a first side of the power semiconductor device, the at least one first doped region and the at least one second doped region are spaced apart from the drift layer by the at least one well region, and an interface between the at least one first doped region and the at least one second doped region is structured.

Abstract: A power semiconductor device comprises a drift layer of a first conductivity type, a source layer of the first conductivity type on the drift layer, with an insulated trench gate electrode which extends through the source layer into the drift layer, and an implant layer of a second conductivity type different than the first conductivity type with a homogeneous doping region having a doping variation of at most 8%. The homogeneous doping region is arranged between the source layer and the drift layer and has a homogeneous doping region thickness of at least 150 nm. A method is provided for producing a power semiconductor device with an insulated trench gate electrode.

Abstract: In one embodiment, the power field-effect transistor (1) comprises: at least two source regions (21) at a top side (20) of a semiconductor body (2), a drain region (22) at a back side (23) of the semiconductor body (2), at least two charge barrier regions (24) in the semiconductor body (2) so that electrically between each one of the source regions (21) and the drain region (22) there is one of the charge barrier regions (24), and a gate electrode (3) located in a trench (4) in the semiconductor body (2), and the charge barrier regions (24) are located adjacent to the trench (4), wherein, next to the trench (4) and seen in a first plane (A) perpendicular with the top side (21) and a main elongation direction (L) of the trench (4), the top side (21) is formed only by the source regions (21).

Abstract: A power semiconductor device is provided. In an embodiment, the power semiconductor device comprises a source region, a channel region in the semiconductor body, and a gate electrode at the channel region. The gate electrode is electrically insulated from the semiconductor body. The channel region is of a second conductivity type different from the first conductivity type. The channel region comprises a first dopant having an activation energy of at most 0.15 eV, and a second dopant having an activation energy of at least 0.3 eV.

Abstract: A superjunction power semiconductor device comprising a substrate, a plurality of core structures and a plurality of annular shell structures. Each core structure has a cylindrical shape extending in a direction perpendicular to a main surface of the substrate and comprising a first semiconductor material of a first conductivity type. Each shell structure surrounds one of the core structures on its outside and comprises a second semiconductor material of a second conductivity type.

Abstract: The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p?/n?/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n?/p?/n+ structures.

Abstract: A power semiconductor device (1) comprising a semiconductor body (2) extending in a vertical direction between a first main surface (21) and a second main surface (22), a trench (4) extending from the first main surface (21) into the semiconductor body (2) in the vertical direction, and an insulated trench gate electrode (3) that is formed on the first main surface (21) and extends into the trench (4) is specified, wherein the trench (4) is subdivided along a main extension direction of the trench (4) in a plurality of segments (41) and the insulated trench gate electrode (3) continuously extends over the plurality of segments (41).

Abstract: A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Abstract: A manufacturing method for a power semiconductor device, comprising forming at least one insulating layer on a surface of a crystalline growth substrate, the at least one insulating layer comprising at least one cavity extending in a lateral direction within the at least one insulating layer; selectively growing a wide bandgap, WBG, semiconductor material within the cavity to form a lateral epi-layer, wherein a surface area of the growth substrate exposed through at least one passage formed between the at least one cavity and the growth substrate is uses as a seed area for epitaxially growing the WBG semiconductor material; and forming at least one semiconductor junction, in particular a pn junction, a np junction or a Schottky junction, within or at an end of the selectively grown WBG semiconductor material.

Abstract: A method comprises providing a semiconductor body with a top side. A mask is applied on the top side of the semiconductor body, wherein the mask comprises at least one first section and at least one second section. The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. A channel region of a first conductivity type is formed in the semiconductor body in the area of the at least one first section. Forming the channel region comprises implanting first-type dopants through the top side into the semiconductor body. An auxiliary layer is deposited on a lateral side of the at least one second section, the lateral side facing towards the at least one first section.

Abstract: A power semiconductor device comprises a semiconductor body with a top side, and a main electrode and an adjacent gate electrode thereon. The semiconductor body comprises a drift layer of a first conductivity type, a base region of a second conductivity type between the drift layer and the top side, a contact region of the first conductivity type between the drift layer and the top side. The contact region adjoins the base region and the top side. The semiconductor body comprises a drift region of the first conductivity type arranged next to and adjoining the base region. The main electrode is in electrical contact with the contact region. The gate electrode at least partially covers a channel portion of the base region, which lies between the contact region and the drift region. At least one of the contact region and the drift region projects beyond the base region.

Abstract: An insulated gate structure includes a wide bandgap material layer having a channel region of a first conductivity type. A gate insulating layer is arranged directly on the channel region and has a first nitride layer that is arranged directly on the channel region. The gate insulating layer has a concentration of carbon atoms that is less than 1018 atoms/cm?3 at a distance of 3 nm from an interface between the wide bandgap material layer and the first nitride layer. An electrically conductive gate electrode layer overlies the gate insulating layer so that the gate electrode layer is separated from the wide bandgap material layer by the gate insulating layer.

Abstract: A power semiconductor device comprises a semiconductor body with a top side, and a main electrode and an adjacent gate electrode thereon. The semiconductor body comprises a drift layer of a first conductivity type, a base region of a second conductivity type between the drift layer and the top side, a contact region of the first conductivity type between the drift layer and the top side. The contact region adjoins the base region and the top side. The semiconductor body comprises a drift region of the first conductivity type arranged next to and adjoining the base region. The main electrode is in electrical contact with the contact region. The gate electrode at least partially covers a channel portion of the base region, which lies between the contact region and the drift region. At least one of the contact region and the drift region projects beyond the base region.

Abstract: The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p?/n?/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n?/p?/n+ structures.

Abstract: A silicon carbide (SiC) planar transistor device includes a SiC semiconductor substrate of a first charge type, a SiC epitaxial layer of the first charge type formed at a top surface of the SiC semiconductor substrate, a source structure of the first charge type formed at a top surface of the SiC epitaxial layer, a drain structure of the first charge type formed at a bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate runner and a gate dielectric that covers at least part of the source structure and the gate runner, and a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure. The channel can be formed by performing a plurality of implantation steps so that the channel region comprises a first region and a second region.

Abstract: A power semiconductor device (10) comprises a semiconductor body (11) which includes a first main surface (12) and a second main surface (13), a gate insulator (14) arranged at the first main surface (12), and a gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) comprises a drift layer (16) of a first conductivity type, a well layer (27) of a second conductivity type being different from the first conductivity type and forming a first junction (18) to the drift layer (16), a source region (20) of the first conductivity type forming a second junction (21) to the well layer (27), and an island region (30) of the second conductivity type attaching the source region (20) such that the source region (20) separates the island region (30) from the well layer (27) in at least 50% of an island surface area of the island region (30) in the semiconductor body (11).

Abstract: The present disclosure relates to a power semiconductor device (100) comprising a silicon carbide semiconductor. SiC. structure (110) comprising a SiC epilayer (112), at least one ohmic contact (120) formed on a first main surface (114) of the SiC structure (110), and at least Schottky barrier contact (130) formed on a second main surface (116) of the SiC structure (110). The at least one Schottky barrier contact (130) comprises a metal layer (136) and a carbon group interlayer (134) arranged between the metal layer (136) and the second main surface (116) of the SiC structure (110). 15 The present disclosure relates to a Schottky barrier diode (400). a vertical field effect transistor, such as a power MOSFET (500), and a method for manufacturing a power semiconductor device (100).

Abstract: The present disclosure relates to a semiconductor device (1) comprising at least one epitaxial layer (2) made from a first semiconductor material comprising carbon and having a [0001] crystallographic axis. At least one implantation area (4) is formed at a sidewall (3a) of the epitaxial layer (2), wherein a normal direction of the sidewall (3a) is perpendicular to the [0001] crystallographic axis. At least one part of the epitaxial layer (2) has a reduced concentration of carbon vacancy (VC) with respect to the first semiconductor material of the at least one epitaxial layer (2) as-grown. The present disclosure further relates to a method for manufacturing a semiconductor device (1), wherein ions are implanted through at least one sidewall (3a) of at least one epitaxial layer (2).

Abstract: A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.