Abstract: A silicon carbide (SiC) planar transistor device includes a SiC semiconductor substrate of a first charge type, a SiC epitaxial layer of the first charge type formed at a top surface of the SiC semiconductor substrate, a source structure of the first charge type formed at a top surface of the SiC epitaxial layer, a drain structure of the first charge type formed at a bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate runner and a gate dielectric that covers at least part of the source structure and the gate runner, and a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure. The channel can be formed by performing a plurality of implantation steps so that the channel region comprises a first region and a second region.

Abstract: A power semiconductor device (10) comprises a semiconductor body (11) which includes a first main surface (12) and a second main surface (13), a gate insulator (14) arranged at the first main surface (12), and a gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) comprises a drift layer (16) of a first conductivity type, a well layer (27) of a second conductivity type being different from the first conductivity type and forming a first junction (18) to the drift layer (16), a source region (20) of the first conductivity type forming a second junction (21) to the well layer (27), and an island region (30) of the second conductivity type attaching the source region (20) such that the source region (20) separates the island region (30) from the well layer (27) in at least 50% of an island surface area of the island region (30) in the semiconductor body (11).

Abstract: The present disclosure relates to a power semiconductor device (100) comprising a silicon carbide semiconductor. SiC. structure (110) comprising a SiC epilayer (112), at least one ohmic contact (120) formed on a first main surface (114) of the SiC structure (110), and at least Schottky barrier contact (130) formed on a second main surface (116) of the SiC structure (110). The at least one Schottky barrier contact (130) comprises a metal layer (136) and a carbon group interlayer (134) arranged between the metal layer (136) and the second main surface (116) of the SiC structure (110). 15 The present disclosure relates to a Schottky barrier diode (400). a vertical field effect transistor, such as a power MOSFET (500), and a method for manufacturing a power semiconductor device (100).

Abstract: The present disclosure relates to a semiconductor device (1) comprising at least one epitaxial layer (2) made from a first semiconductor material comprising carbon and having a [0001] crystallographic axis. At least one implantation area (4) is formed at a sidewall (3a) of the epitaxial layer (2), wherein a normal direction of the sidewall (3a) is perpendicular to the [0001] crystallographic axis. At least one part of the epitaxial layer (2) has a reduced concentration of carbon vacancy (VC) with respect to the first semiconductor material of the at least one epitaxial layer (2) as-grown. The present disclosure further relates to a method for manufacturing a semiconductor device (1), wherein ions are implanted through at least one sidewall (3a) of at least one epitaxial layer (2).

Abstract: A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

Abstract: A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, a n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.

Abstract: The present disclosure relates to a method for forming an ohmic contact on a wide-bandgap semiconductor device comprising: shallow implanting a dopant through a first surface of a wide-bandgap semiconductor device using an implantation energy of less than 15 keV to form at least one interface region of a wide-bandgap semiconductor material, thermal treatment of the interface region comprising the implanted dopant at a temperature below 1100° C., and depositing a metal material on top of the at least one interface region to form at least one ohmic contact region. The present disclosure further relates to a wide-bandgap semiconductor device comprising a semiconductor body or epitaxial layer comprising a wide-bandgap semiconductor material, at least one interface region which is doped and arranged within the wide-bandgap semiconductor material, and at least one ohmic contact region arranged on top of the at least one interface region.

Abstract: One embodiment provides a power semiconductor device that includes a semiconductor body. A source region of a first conductivity type is disposed at a top side the semiconductor body. A channel region of a second conductivity type is disposed in the semiconductor body below the source region and a drift region of the first conductivity type is disposed in the semiconductor body below the channel region. A trench extends from the top side through the source region and through the channel region and ending in the drift region. As seen in a top view of the top side, the trench comprises a plurality of branch-offs. A gate electrode is disposed within the trench and a shield region of the second conductivity type is located at least partially below a branch-off of the trench.

Abstract: A power semiconductor device (1) is provided, comprising a drift layer (2) of a first conductivity type, at least two well regions (3) of a second conductivity type being different from the first conductivity type, and at least one intermediate region (4), wherein the at least two well regions (3) and the at least one intermediate region (4) are provided within the drift layer (2) at a first side, the at least one intermediate region (4) is provided between the at least two well regions (3), and the at least one intermediate region (4) comprises at least one first doped region (5) of the first conductivity type and at least one second doped region (6) of the second conductivity type.

Abstract: Disclosed is a vertical silicon carbide power MOSFET with a 4H-SiC substrate of n+-type as drain and a 4H-Si C epilayer of n?-type, epitaxially grown on the 4H-SiC substrate acting as drift region and a source region of p++-type, a well region of p-type, a channel region of p-type and a contact region of n++-type implanted into the drift region and a metal gate insulated from the source and drift region by a gate-oxide. A high mobility layer with a vertical thickness in a range 0.1 nm to 50 nm exemplarily in the range of 0.5 nm to 10 nm is provided at the interface between the 4H-SiC epilayer and the gate-oxide.

Abstract: A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Abstract: A silicon carbide power device having a low on-resistance Ron and a method for manufacturing the same are provided. The silicon carbide power device comprises a first conductivity-type substrate, a plurality of silicon carbide layer stacks, a continuous insulating layer and a gate electrode layer. Each silicon carbide layer stack comprises the following layers stacked on the substrate: a first conductivity-type drain layer, a second conductivity-type channel layer and a first conductivity-type source layer. A plurality of first insulating layer portions laterally cover and surround at least the drain layer and the channel layer of each silicon carbide layer stack. Each point of each channel layer is laterally sandwiched between two opposing portions of the gate electrode layer, wherein the two opposing portions have a distance (d) of less than 2 ?m along a straight line extending through that point of that channel layer.

Abstract: Semiconductor device having first and second main electrodes with gate electrode layer inbetween, semiconductor layer stack between and in electrical contact with the first and second main electrodes having differently doped semiconductor layers. At least two semiconductor layers differ in their conductivity type and/or their doping concentration. Pillar-shaped or fin-shaped regions run through the gate electrode layer, each having a contact layer arranged at the first main electrode with a first doping concentration and a first conductivity type. Each contact layer extends to a side of the gate electrode layer facing the first main electrode, the contact layers of adjacent pillar-shaped or fin-shaped regions merge on the side of the gate electrode layer facing the first main electrode so that the contact layers of adjacent pillar-shaped or fin-shaped regions are arranged continuously on the side of the gate electrode layer facing the first main electrode.

Abstract: A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.

Abstract: A power semiconductor device (1) comprising a semiconductor body (2) extending in a vertical direction between a first main surface (21) and a second main surface (22), a trench (4) extending from the first main surface (21) into the semiconductor body (2) in the vertical direction, and an insulated trench gate electrode (3) that is formed on the first main surface (21) and extends into the trench (4) is specified, wherein the trench (4) is subdivided along a main extension direction of the trench (4) in a plurality of segments (41) and the insulated trench gate electrode (3) continuously extends over the plurality of segments (41).

Abstract: In at least one embodiment, the power semiconductor device (1) comprises a semiconductor body (2), and a protection layer (3) at the semiconductor body (2), wherein the protection layer (3) comprises a material having a surface energy of at most 0.1 mJ/m2, and the protection layer (3) comprises a geometric structuring (33) having a feature size (F) of at least 0.04 ?m and of at most 0.1 mm, seen in top view of the protection layer (3).

Abstract: In one embodiment, the power field-effect transistor (1) comprises: at least two source regions (21) at a top side (20) of a semiconductor body (2), a drain region (22) at a back side (23) of the semiconductor body (2), at least two charge barrier regions (24) in the semiconductor body (2) so that electrically between each one of the source regions (21) and the drain region (22) there is one of the charge barrier regions (24), and a gate electrode (3) located in a trench (4) in the semiconductor body (2), and the charge barrier regions (24) are located adjacent to the trench (4), wherein, next to the trench (4) and seen in a first plane (A) perpendicular with the top side (21) and a main elongation direction (L) of the trench (4), the top side (21) is formed only by the source regions (21).

Abstract: In at least one embodiment, the power semiconductor device 1) involves a semiconductor body (2), at least one source region (21) in the semiconductor body (2), a gate electrode (3) at the semiconductor body (2), a gate insulator (4, 41, 42) between the semiconductor body (2) and the gate electrode (3), and at least one well region (22) at the at least one source region (21) and at the gate insulator (4, 41, 42), wherein the gate insulator (4, 41, 42) has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator (4, 41, 42) at a specific location thereof, and the dielectric capacitance is larger at the at least one well region (22) than in remaining regions of the gate insulator (4, 42).

Abstract: A power semiconductor device is provided. In an embodiment, the power semiconductor device comprises a source region, a channel region in the semiconductor body, and a gate electrode at the channel region. The gate electrode is electrically insulated from the semiconductor body. The channel region is of a second conductivity type different from the first conductivity type. The channel region comprises a first dopant having an activation energy of at most 0.15 eV, and a second dopant having an activation energy of at least 0.3 eV.

Abstract: A power semiconductor device comprises a drift layer of a first conductivity type, a source layer of the first conductivity type on the drift layer, with an insulated trench gate electrode which extends through the source layer into the drift layer, and an implant layer of a second conductivity type different than the first conductivity type with a homogeneous doping region having a doping variation of at most 8%. The homogeneous doping region is arranged between the source layer and the drift layer and has a homogeneous doping region thickness of at least 150 nm. A method is provided for producing a power semiconductor device with an insulated trench gate electrode.