Patents by Inventor Lars Knoll

Lars Knoll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180350943
    Abstract: A wide bandgap semiconductor device is comprising an (n?) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 6, 2018
    Inventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
  • Publication number: 20180350977
    Abstract: A power semiconductor device includes a plurality of vertical field effect transistor cells arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction, wherein in each vertical field effect transistor cell a body region is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other. In each row of vertical field effect transistor cells the body regions are separated from each other in the first direction by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction. The first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 6, 2018
    Inventors: Lars Knoll, Renato Minamisawa
  • Publication number: 20180286963
    Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
  • Publication number: 20180212071
    Abstract: A semiconductor power rectifier with increased surge current capability is described, which has a semiconductor layer having a first main side and a second main side opposite to the first main side. The semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 ?m and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 26, 2018
    Inventors: Andrei Mihaila, Munaf Rahimo, Renato Minamisawa, Lars Knoll, Liutauras Storasta
  • Publication number: 20150024586
    Abstract: In the method for producing a monocrystalline metal-semiconductor compound on the surface of a semiconducting functional layer, initially a supply layer comprising the metal is applied to the functional layer. Thereafter, the reaction between the metal and the functional layer is triggered by way of annealing. The supply layer ends at no greater than a layer thickness of 5 nm from the surface of the functional layer, or it transitions at no greater than this layer thickness into a region in which the metal diffuses more slowly than in the region that directly adjoins the functional layer. This measure advantageously allows diffusion flow of the metal into the functional layer to be prevented. This depends precisely on whether the metal-semiconductor compound is monocrystalline.
    Type: Application
    Filed: February 16, 2013
    Publication date: January 22, 2015
    Inventors: Qing-Tai Zhao, Lars Knoll, Siegfried Mantl