Patents by Inventor Lars Knoll
Lars Knoll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11031473Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.Type: GrantFiled: September 3, 2019Date of Patent: June 8, 2021Assignee: ABB POWER GRIDS SWITZERLAND AGInventors: Friedhelm Bauer, Lars Knoll, Marco Bellini, Renato Minamisawa, Umamaheswara Vemulapati
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Publication number: 20210043735Abstract: An embodiment provides a power semiconductor device having a low on-state resistance while avoiding any short channel effects and having a low subthreshold slope. The embodiment provides a trench power semiconductor device, which comprises a compensation layer of a first conductivity type, wherein the compensation layer is extending on a gate insulation layer between a source layer of the first conductivity type and a substrate layer of the first conductivity type directly adjacent to a channel region of a second conductivity type.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Renato Minamisawa, Lars Knoll
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Publication number: 20210020753Abstract: A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.Type: ApplicationFiled: March 5, 2019Publication date: January 21, 2021Inventors: Andrei Mihaila, Lars Knoll, Lukas Kranz
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Patent number: 10553437Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.Type: GrantFiled: June 4, 2018Date of Patent: February 4, 2020Assignee: ABB Schweiz AGInventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
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Publication number: 20200006496Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.Type: ApplicationFiled: September 3, 2019Publication date: January 2, 2020Inventors: Friedhelm Bauer, Lars Knoll, Marco Bellini, Renato Minamisawa, Umamaheswara Vemulapati
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Patent number: 10516022Abstract: A wide bandgap semiconductor device is comprising an (n?) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.Type: GrantFiled: June 4, 2018Date of Patent: December 24, 2019Assignee: ABB Schweiz AGInventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
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Publication number: 20190363166Abstract: The power semiconductor device according to the invention is a trench power field effect transistor, at all locations within a channel region a first local doping concentration is less than 1·1017 cm?3. In the base layer a second local doping concentration is at least 1·1017 cm?3 at all locations within the base layer. In the invention a channel length LCH, fulfils the following inequation: L CH > 4 ? ? ( ( ? CH ? t CH ? t GI ) ? GI ) , wherein ?CH is a permittivity of the channel region, ?GI is a permittivity of the gate insulation layer, tCH is a thickness of the channel region in a direction perpendicular to an interface between the gate insulation layer and the channel region, and tGI is a thickness of the gate insulation layer in a direction perpendicular to the interface between the gate insulation layer and the channel region.Type: ApplicationFiled: December 31, 2018Publication date: November 28, 2019Inventors: Lars Knoll, Renato Minamisawa
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Patent number: 10490658Abstract: A power semiconductor device includes a plurality of vertical field effect transistor cells arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction, wherein in each vertical field effect transistor cell a body region is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other. In each row of vertical field effect transistor cells the body regions are separated from each other in the first direction by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction. The first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction.Type: GrantFiled: August 2, 2018Date of Patent: November 26, 2019Assignee: ABB Schweiz AGInventors: Lars Knoll, Renato Minamisawa
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Patent number: 10361082Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.Type: GrantFiled: June 4, 2018Date of Patent: July 23, 2019Assignee: ABB Schweiz AGInventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
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Publication number: 20190035928Abstract: The present application provides a power semiconductor device having a low on-state resistance while avoiding any short channel effects and having a low subthreshold slope. To attain this object the invention provides a trench power semiconductor device, which includes a compensation layer of a first conductivity type, wherein the compensation layer is extending on a gate insulation layer between a source layer of the first conductivity type and a substrate layer of the first conductivity type directly adjacent to a channel region of a second conductivity type, and wherein: L ch > 4 ? ? ( ? CR ? t COMP ? t GI ? GI ) . In the above inequation Lch is a channel length, ?CR is a permittivity of the channel region, ?GI is a permittivity of the gate insulation layer, tCOMP is a thickness of the compensation layer and tGI is a thickness of the gate insulation layer.Type: ApplicationFiled: October 2, 2018Publication date: January 31, 2019Inventors: Renato Minamisawa, Lars Knoll
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Patent number: 10164126Abstract: A semiconductor power rectifier with increased surge current capability is described. A semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 ?m and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.Type: GrantFiled: January 3, 2018Date of Patent: December 25, 2018Assignee: ABB Schweiz AGInventors: Andrei Mihaila, Munaf Rahimo, Renato Minamisawa, Lars Knoll, Liutauras Storasta
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Publication number: 20180350977Abstract: A power semiconductor device includes a plurality of vertical field effect transistor cells arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction, wherein in each vertical field effect transistor cell a body region is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other. In each row of vertical field effect transistor cells the body regions are separated from each other in the first direction by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction. The first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction.Type: ApplicationFiled: August 2, 2018Publication date: December 6, 2018Inventors: Lars Knoll, Renato Minamisawa
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Publication number: 20180350943Abstract: A wide bandgap semiconductor device is comprising an (n?) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.Type: ApplicationFiled: June 4, 2018Publication date: December 6, 2018Inventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
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Publication number: 20180350602Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.Type: ApplicationFiled: June 4, 2018Publication date: December 6, 2018Inventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
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Publication number: 20180286963Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.Type: ApplicationFiled: June 4, 2018Publication date: October 4, 2018Inventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
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Publication number: 20180212071Abstract: A semiconductor power rectifier with increased surge current capability is described, which has a semiconductor layer having a first main side and a second main side opposite to the first main side. The semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 ?m and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.Type: ApplicationFiled: January 3, 2018Publication date: July 26, 2018Inventors: Andrei Mihaila, Munaf Rahimo, Renato Minamisawa, Lars Knoll, Liutauras Storasta
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Publication number: 20150024586Abstract: In the method for producing a monocrystalline metal-semiconductor compound on the surface of a semiconducting functional layer, initially a supply layer comprising the metal is applied to the functional layer. Thereafter, the reaction between the metal and the functional layer is triggered by way of annealing. The supply layer ends at no greater than a layer thickness of 5 nm from the surface of the functional layer, or it transitions at no greater than this layer thickness into a region in which the metal diffuses more slowly than in the region that directly adjoins the functional layer. This measure advantageously allows diffusion flow of the metal into the functional layer to be prevented. This depends precisely on whether the metal-semiconductor compound is monocrystalline.Type: ApplicationFiled: February 16, 2013Publication date: January 22, 2015Inventors: Qing-Tai Zhao, Lars Knoll, Siegfried Mantl