Abstract: A digital audio processor for a digital audio receiver having an improved automute sequence is disclosed. The digital audio processor includes automute detection circuitry that monitors the amplitude of digital audio signals before and after the application of digital filters by digital audio processing circuitry. The amplitude of the input signals are compared against a first threshold level, while the amplitude of the output signals are compared against a second threshold level. In response to the amplitude of the input signals for all of the audio channels falling below the first threshold for a selected time period, a gain stage in each channel ramps down the volume to a mute level, and pulse-width-modulation circuitry is disabled. If the output signal amplitude falls below a second threshold for a channel, the pulse-width-modulation circuitry for that channel is disabled. Hysteresis for the input signal amplitude is preferably added into the automute exit determination.

Abstract: Overcurrent and overload protection for the power output of a pulse-width-modulated digital audio system is disclosed. The overcurrent protection circuitry includes a latch that is set in responsive to output current from the power output stage that exceeds an overcurrent threshold; the output of the latch gates the pulse-width-modulated control signal to block power output for the remainder of the current pulse-width-modulated cycle; upon the end of the cycle, or the beginning of the next, the latch is cleared to enable power output in that next cycle. Overload protection is provided by circuitry including counters for counting the relative number of overcurrent cycles to normal, non-overcurrent cycles, and generating an overload signal to block power output in the event of too frequent overcurrent cycles.

Abstract: One embodiment of an apparatus for filtering an electrical signal includes a loop filter with an input and an output that applies a transfer function to a signal at the input. The transfer function has substantially no real part. The loop filter has a dominant pole placed substantially at or above an upper frequency in the frequency range of interest for the loop filter.

Abstract: Asynchronous sample rate conversion for use in a digital audio receiver is disclosed. Different algorithms are applied for the upsampling and downsampling cases. In the upsampling case, the input signal is upsampled and filtered, before the application of a finite impulse response (FIR) filter. In the downsampling case, the input signal is filtered by an FIR filter, and then filtered and downsampled. The FIR coefficients of the fractional delay FIR filter are calculated by evaluation of polynomial expressions over intervals of the filter impulse response, at times corresponding to the input sample points.

Abstract: Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM) audio signals. The modulation circuitry includes a duration quantizer function (32) that generates a sequence of duration values d(k) from received PCM samples, quantized to integer multiples of periods of a master PWM clock (CLKpwm). The duration quantizer function also produces a feedback PCM value x(k) from each quantized duration value d(k) that is applied to a loop filter (36), the output of which modifies the received PCM sample stream to suppress quantization noise. Transient effects caused by modulation or abrupt changes in the desired PWM period are suppressed by digitally filtering (34; 134) the PWM period sample stream.

Abstract: A multiple-channel audio processor (10) and an associated plurality of power stages (22) in an audio system are disclosed. The audio processor (10) includes a plurality of audio amplifier channels (22), each of which includes a pulse-code-modulation (PCM) to pulse-width-modulation (PWM) conversion function (25), which generates PWM signals for application to the plurality of power stages (22). The audio amplifier channels (20) each also include an interchannel delay function (28) for delaying the PWM edges relative to other channels (20), for reducing noise. The audio amplifier channels (20) each also include delay adjust circuitry (32) for gradually increasing and decreasing the interchannel delay of the channel (20) on startup and shutdown. This permits a single control terminal (VALID) at the processor to globally enable and disable all of the power stages (22).

Abstract: Asynchronous sampling rate converter using multistage oversampling with final stage polyphase filter coefficients approximated by polynomials of the filter index. The approximation polynomial coefficients occupy smaller memory than the polyphase filter coefficients being approximated.

Abstract: A multiple-channel audio processor (10) and an associated plurality of power stages (22) in an audio system are disclosed. The audio processor (10) includes a plurality of audio amplifier channels (22), each of which includes a pulse-code-modulation (PCM) to pulse-width-modulation (PWM) conversion function (25), which generates PWM signals for application to the plurality of power stages (22). The audio amplifier channels (20) each also include an interchannel delay function (28) for delaying the PWM edges relative to other channels (20), for reducing noise. The audio amplifier channels (20) each also include delay adjust circuitry (32) for gradually increasing and decreasing the interchannel delay of the channel (20) on startup and shutdown. This permits a single control terminal (VALID) at the processor to globally enable and disable all of the power stages (22).

Abstract: System for pulse-width-modulated class D audio amplifiers. In one preferred embodiment an adder is described to generate a difference signal responsive to an input signal and a feedback signal, a pulse-width-modulator coupled to the adder to compare the difference signal to a reference signal and produce a pulse-width-modulated signal based on the comparing, a filter coupled to an output of the pulse-width-modulator, and a loop filter having a first input coupled to the output of the filter and a second input coupled to the input of the filter, the loop filter to generate a feedback signal by applying transfer functions to signals at its inputs. The loop transfer function of the amplifier is minimum aliasing error transfer function. The minimum aliasing error properties provide low distortion and taking the feedback from the output of the filter reduces high frequency output impedance.

Abstract: One embodiment of an apparatus for filtering an electrical signal includes a loop filter with an input and an output that applies a transfer function to a signal at the input. The transfer function has substantially no real part. The loop filter has a dominant pole placed substantially at or above an upper frequency in the frequency range of interest for the loop filter.

Abstract: Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM) audio signals. The modulation circuitry includes a duration quantizer function (32) that generates a sequence of duration values d(k) from received PCM samples, quantized to integer multiples of periods of a master PWM clock (CLKpwm). The duration quantizer function also produces a feedback PCM value x(k) from each quantized duration value d(k) that is applied to a loop filter (36), the output of which modifies the received PCM sample stream to suppress quantization noise. Transient effects caused by modulation or abrupt changes in the desired PWM period are suppressed by digitally filtering (34; 134) the PWM period sample stream.

Abstract: A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47).

Abstract: A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.

Abstract: A class AD audio amplifier system (10) with reduced noise capability in muting and unmuting events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. When the system is muted, a common mode voltage (CM_RAMP) is applied to the inputs of the comparators (39A, 39B; 52+ 52?) to suppress the duty cycle at the amplifier output, preferably to a zero duty cycle. In the transition from a muted state to an unmuted state, the common mode voltage (CM_RAMP) is ramped from the suppressing voltage to zero common mode voltage, permitting the duty cycle of the complementary PWM signals to gradually increase, thus reducing clicks and pops.

Abstract: A system and method are provided for stopping a quantized signal from a noise-shaper with a significantly reduced inband transient, compared to a traditional random stop of a noise-shaped signal. The noise-shaped signal is stopped at a favorable time controlled by a detector that monitors the noise-shaped signal. The detector indicates the occurrence of a good time to stop the noise-shaper such that the transient due to the stop is minimized in a fashion that substantially reduces the inband disturbance.

Abstract: A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.

Abstract: An audio system includes a switch mode amplifier that provides an output signal at an output for driving a load based on at least one control signal. A control system provides the at least one control signal to control the amplifier according to an operating mode of the audio system. In a first mode, the control system providing the at least one control signal to actively control an equivalent output impedance at the output of the amplifier, gradually adjusting the equivalent output impedance from a high-impedance state to a low impedance state, so as to mitigate a voltage drop across the load (e.g., including one or more speakers) when the amplifier is activated to a second mode corresponding to the low impedance state.

Abstract: System for pulse-width-modulated class D audio amplifiers. In one preferred embodiment an adder is described to generate a difference signal responsive to an input signal and a feedback signal, a pulse-width-modulator coupled to the adder to compare the difference signal to a reference signal and produce a pulse-width-modulated signal based on the comparing, a filter coupled to an output of the pulse-width-modulator, and a loop filter having a first input coupled to the output of the filter and a second input coupled to the input of the filter, the loop filter to generate a feedback signal by applying transfer functions to signals at its inputs. The loop transfer function of the amplifier is minimum aliasing error transfer function. The minimum aliasing error properties provide low distortion and taking the feedback from the output of the filter reduces high frequency output impedance.

Abstract: A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47).

Abstract: The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).