Abstract: A digital audio processor (20) for a digital audio receiver (21) having an improved automute sequence is disclosed. The digital audio processor (20) includes automute detection circuitry (42) that monitors the amplitude of digital audio signals before and after the application of digital filters by digital audio processing circuitry (20d). The amplitude of the input signals are compared against a first threshold level, while the amplitude of the output signals are compared against a second threshold level. In response to the amplitude of the input signals for all of the audio channels (44) falling below the first threshold for a selected time period, a gain stage (50) in each channel ramps down the volume to a mute level, and pulse-width-modulation circuitry (54) is disabled. If the output signal amplitude falls below a second threshold for a channel, the pulse-width-modulation circuitry (54) for that channel is disabled.

Abstract: An audio system includes a switch mode amplifier that provides an output signal at an output for driving a load based on at least one control signal. A control system provides the at least one control signal to control the amplifier according to an operating mode of the audio system. In a first mode, the control system providing the at least one control signal to actively control an equivalent output impedance at the output of the amplifier, gradually adjusting the equivalent output impedance from a high-impedance state to a low impedance state, so as to mitigate a voltage drop across the load (e.g., including one or more speakers) when the amplifier is activated to a second mode corresponding to the low impedance state.

Abstract: A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47).

Abstract: Overcurrent and overload protection for the power output of a pulse-width-modulated digital audio system is disclosed. The overcurrent protection circuitry includes a latch that is set in responsive to output current from the power output stage that exceeds an overcurrent threshold; the output of the latch gates the pulse-width-modulated control signal to block power output for the remainder of the current pulse-width-modulated cycle; upon the end of the cycle, or the beginning of the next, the latch is cleared to enable power output in that next cycle. Overload protection is provided by circuitry including counters for counting the relative number of overcurrent cycles to normal, non-overcurrent cycles, and generating an overload signal to block power output in the event of too frequent overcurrent cycles.

Abstract: A digital audio processor (20) is disclosed, in which digital filter coefficients associated with a plurality of sampling frequencies are stored in a plurality of coefficient memory banks (55). A controller in the digital audio processor (20) selects one of the coefficient memory banks (55) for use in the digital signal processing channels (44). In a manual mode, this selection is in response to a manual selection entry in a bank control register (41). In an automatic mode, indicated by a specific entry in the bank control register (41), sample rate detector circuitry (54) detects the sampling frequency relative to an external reference, such as a crystal (XTL); the appropriate one of the coefficient memory banks (55) is then selected based on sampling frequency associations stored in rate select register (43) in the controller (40).

Abstract: A digital audio system (2) including a digital audio amplifier (8) with reduced AM interference is disclosed. The digital audio amplifier (8) includes a pulse-width-modulation (PWM) processor (10) in which a digital datastream at a sampling frequency is upsampled by an interpolation filter (16) to a multiple of the sampling frequency. The upsampled datastream is applied to a sample rate converter (17) which resamples the upsampled datastream to produce a datastream at a converted sampling frequency, or PWM frame rate. The converted datastream is then applied to pulse-width-modulation circuitry (21) which generates a PWM signal at the PWM frame rate. Clock circuitry (25) generates clock signals, to the sample rate converter (17), responsive to a sample rate conversion ratio that is associated with the AM tuned frequency.

Abstract: A class AD audio amplifier system (10) with DC output detection logic (26) is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which includes a pulse-width-modulator (PWM) (24). The DC detection logic (26) includes a sigma-delta modulator (60) and a digital low-pass filter (62) that monitors the PWM output signals from the PWM modulators (24). The sigma-delta modulator (60) operates at a first clock frequency, while the low-pass filter (62) operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators (24) are disabled to prevent unsafe conditions in the system (10).

Abstract: A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

Abstract: A multiple-channel audio processor (10) and an associated plurality of power stages (22) in an audio system are disclosed. The audio processor (10) includes a plurality of audio amplifier channels (22), each of which includes a pulse-code-modulation (PCM) to pulse-width-modulation (PWM) conversion function (25), which generates PWM signals for application to the plurality of power stages (22). The audio amplifier channels (20) each also include an interchannel delay function (28) for delaying the PWM edges relative to other channels (20), for reducing noise. The audio amplifier channels (20) each also include delay adjust circuitry (32) for gradually increasing and decreasing the interchannel delay of the channel (20) on startup and shutdown. This permits a single control terminal (VALID) at the processor to globally enable and disable all of the power stages (22).

Abstract: A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry on the front-end digital modulator chip. The front-end dead time control circuitry adaptively adjusts timing of the output PWM control signals 124 to optimize performance and power consumption, i.e. operate with minimum dead time for all transitions. The front-end dead time control circuitry controls all propagation delays associated with the digital switching amplifier system 100.

Abstract: The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).

Abstract: A class-D amplifier circuit (30; 30?) providing improved open-loop error for base-band frequencies, such as the audio band, is disclosed. The amplifier circuit (30; 30?) includes a comparator (35) for generating a pulse-width-modulated output signal that is applied to an output power stage (37). An LC filter (32) is at the output of the power stage (37). The amplifier circuit (30; 30?) includes a loop filter having multiple feedback loop paths, with at least one feedback loop path coupled to the output of the power stage (37), and optionally, at least one feedback loop path coupled to the output of the LC filter (32). The transfer function (Hmae(s)) of the loop filter has a real part that has a much steeper slope (on the order of 80 dB/decade) at frequencies above the pulse-width-modulation switching frequency than the slope of its magnitude characteristic at frequencies below this switching frequency.

Abstract: A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry on the front-end digital modulator chip. The front-end dead time control circuitry adaptively adjusts timing of the output PWM control signals 124 to optimize performance and power consumption, i.e. operate with minimum dead time for all transitions. The front-end dead time control circuitry controls all propagation delays associated with the digital switching amplifier system 100.

Abstract: A class AD audio amplifier system (10) with reduced noise capability in muting and unmuting events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. When the system is muted, a common mode voltage (CM_RAMP) is applied to the inputs of the comparators (39A, 39B; 52+ 52?) to suppress the duty cycle at the amplifier output, preferably to a zero duty cycle. In the transition from a muted state to an unmuted state, the common mode voltage (CM_RAMP) is ramped from the suppressing voltage to zero common mode voltage, permitting the duty cycle of the complementary PWM signals to gradually increase, thus reducing clicks and pops.

Abstract: A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52?) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47).

Abstract: A class AD audio amplifier system (10) with DC output detection logic (26) is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which includes a pulse-width-modulator (PWM) (24). The DC detection logic (26) includes a sigma-delta modulator (60) and a digital low-pass filter (62) that monitors the PWM output signals from the PWM modulators (24). The sigma-delta modulator (60) operates at a first clock frequency, while the low-pass filter (62) operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators (24) are disabled to prevent unsafe conditions in the system (10).

Abstract: A class-D amplifier circuit (30; 30?) providing improved open-loop error for base-band frequencies, such as the audio band, is disclosed. The amplifier circuit (30; 30?) includes a comparator (35) for generating a pulse-width-modulated output signal that is applied to an output power stage (37). An LC filter (32) is at the output of the power stage (37). The amplifier circuit (30; 30?) includes a loop filter having multiple feedback loop paths, with at least one feedback loop path coupled to the output of the power stage (37), and optionally, at least one feedback loop path coupled to the output of the LC filter (32). The transfer function (Hmae(s)) of the loop filter has a real part that has a much steeper slope (on the order of 80 dB/decade) at frequencies above the pulse-width-modulation switching frequency than the slope of its magnitude characteristic at frequencies below this switching frequency.

Abstract: A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

Abstract: An error model can be utilized to mitigate errors associated with a conversion system, such as an analog-to-digital or digital-to analog converter. The error model is adaptively calibrated to approximate error characteristics associated with at least a portion of the conversion system, such as a digital-to analog converter. The error model can be generated on-line during system operation or off-line to improve performance of various types of signal converters and systems using such signal converters.

Abstract: A system and method for reducing audible turn-on and turn-off transients in switching amplifiers employs a frequency shaped start sequence in front of a modulated zero-signal or a frequency shaped stop sequence following a modulated zero-signal.