Abstract: A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors.

Abstract: An electronic device comprises a first feedback circuit operatively connected to an amplitude detector and a first control input of an oscillator. The first feedback circuit is configured to control an amplitude of an output of the oscillator by continuously applying a first control signal to the first control input in response to an amplitude detected by the amplitude detector. The electronic device further comprises a second feedback circuit operatively connected to the amplitude detector and a second control input of the oscillator. The second feedback circuit is configured to modify one or more amplitude regulating parameters of the oscillator by providing a second control signal in response to the amplitude being beyond an upper or lower amplitude threshold, and refrain from modifying the one or more amplitude regulating parameters when the amplitude is within the upper and lower amplitude thresholds.

Abstract: Systems and methods are disclosed herein that relate to a wireless device that intelligently uses different reference crystal oscillators (XOs) for a Phase Locked Loop(s) (PLL(s)) in a transceiver of the wireless device. Embodiments of a method of operation of a wireless device comprising a first XO that operates at a first reference frequency and a second XO that operates at a second reference frequency that is greater than the first reference frequency are disclosed. In some embodiments, the method of operation of the wireless devices comprises deciding whether to configure a receiver of the wireless device to use the first XO or the second XO and configuring the receiver of the wireless device to use the first XO or the second XO in accordance with the decision.

Abstract: A method of scheduling wireless data transmissions between a mobile terminal (701) and a base station using multiple component carrier signals is disclosed. The method comprises the steps of: receiving in the mobile terminal information from the base station indicating available component carriers; detecting in the mobile terminal at least one dynamic parameter indicative of the mobile terminal's current ability to handle component carriers having non-contiguous bandwidths; determining in the mobile terminal in dependence of the at least one dynamic parameter which of the available component carriers to utilize; and transmitting from the mobile terminal to the base station information indicating the component carriers determined to utilize.

Abstract: A beamforming apparatus (10) performs beamforming via a plurality of antenna elements (12) by using per-branch sign reversal circuits (16) that approximate the per-branch phase values associated with a particular beam direction or shape by selectively reversing or not reversing the polarities of the individual branch signals (18). Eliminating continuous-valued or high-resolution phasing control from the branch circuits (14) that are fed into or from the respective antenna elements (12) simplifies the branch circuitry, thereby reducing the physical space needed for the branch circuits (14) and reducing loss and noise within the branch circuits (14). Further, operating the plurality of antenna elements (12) as two or more groups (24) and controlling the differential phase between the groups (24) advantageously reduces the errors arising from the approximation of the per-branch phase values.

Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: An apparatus for a multi-antenna transceiver is disclosed. The multi-antenna transceiver has a plurality of antenna elements connected to respective transceiver chains. Each transceiver chain includes a frequency converter operated using a respective local oscillator signal provided by a respective phase-locked loop. The apparatus includes a controller configured to cause control of the respective phase-locked loop of one or more transceiver chain to generate the respective local oscillator signal with a respective phase offset for mitigation of local oscillator leakage through the frequency converter. In some embodiments, the controller is further configured to cause, for each transceiver chain with a non-zero respective phase offset, a corresponding phase adjustment of a signal for frequency conversion. Corresponding multi-antenna transceivers, wireless communication devices and methods are also disclosed.

Abstract: A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors.

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) is disclosed, which is configured to receive an analog input signal and provide a digital output signal. The SAR ADC comprises a capacitor bank for successively providing a plurality of signal levels based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal. Furthermore, the SAR ADC comprises controlling circuitry configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal. In some embodiments, a respective selector of each capacitor of the capacitor bank is controlled to charge the capacitor using either the sample value of the analog input signal or the sample value of an opposed version of the analog input signal.

Abstract: An electronic device comprises a first feedback circuit operatively connected to an amplitude detector and a first control input of an oscillator. The first feedback circuit is configured to control an amplitude of an output of the oscillator by continuously applying a first control signal to the first control input in response to an amplitude detected by the amplitude detector. The electronic device further comprises a second feedback circuit operatively connected to the amplitude detector and a second control input of the oscillator. The second feedback circuit is configured to modify one or more amplitude regulating parameters of the oscillator by providing a second control signal in response to the amplitude being beyond an upper or lower amplitude threshold, and refrain from modifying the one or more amplitude regulating parameters when the amplitude is within the upper and lower amplitude thresholds.

Abstract: A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

Abstract: A radio transmitter circuit (10) for transmitting signals within an uplink or sidelink frequency band of a cellular communications system is disclosed. It comprises a signal-generation circuit (20) configured to generate a transmission signal to be transmitted, and a radio front-end circuit (30), connected to the signal-generation circuit (20) at an input of the radio front-end circuit (30), for receiving the transmission signal, and configured to be connected to an antenna (40) at an output of the radio front-end circuit and to transmit the transmission signal to a remote node via said antenna (40). The signal-generation circuit (20) is configured to select a distortion function (D1, D2) based on a location of an allocated radio frequency resource, within said uplink or sidelink frequency band, for the transmission signal. Furthermore, the signal-generation circuit (20) is configured to generate an intermediate transmission signal, based on information to be transmitted in the transmission signal.

Abstract: Systems and methods are disclosed herein that relate to a wireless device that intelligently uses different reference crystal oscillators (XOs) for a Phase Locked Loop(s) (PLL(s)) in a transceiver of the wireless device. Embodiments of a method of operation of a wireless device comprising a first XO that operates at a first reference frequency and a second XO that operates at a second reference frequency that is greater than the first reference frequency are disclosed. In some embodiments, the method of operation of the wireless devices comprises deciding whether to configure a receiver of the wireless device to use the first XO or the second XO and configuring the receiver of the wireless device to use the first XO or the second XO in accordance with the decision.

Abstract: An ADC includes a plurality of sub ADCs configured to operate in a time-interleaved manner and a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs. The ADC includes a test signal generation circuit configured to generate a test signal for calibration of the ADC. The sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal. The sampling circuit includes an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit. The first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase.

Abstract: A method of a wireless transmitter is disclosed. The method is for mitigation of distortion caused by non-linear hardware components of the transmitter, wherein mitigation of distortion comprises mitigating at least one intermodulation component, wherein the transmitter is configured to process an input signal having an input signal spectrum, and wherein the transmitter comprises two or more signal branches, each signal branch comprising a respective non-linear hardware component. The method comprises modifying the input signal for a first one of the signal branches by applying a first phase shift to a first part of the input signal spectrum, wherein the first phase shift has a first sign and a first absolute value, and applying a second phase shift to a second part of the input signal spectrum. The second phase shift has a second sign which is opposite to the first sign, and a second absolute value which is equal to the first absolute value. The first and second parts are non-overlapping.

Abstract: A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M?2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N?1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak1) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme.

Abstract: Systems and methods are disclosed herein that relate to a wireless device that intelligently uses different reference crystal oscillators (XOs) for a Phase Locked Loop(s) (PLL(s)) in a transceiver of the wireless device. Embodiments of a method of operation of a wireless device comprising a first XO that operates at a first reference frequency and a second XO that operates at a second reference frequency that is greater than the first reference frequency are disclosed. In some embodiments, the method of operation of the wireless devices comprises making a decision as to whether to configure a receiver of the wireless device to use the first XO or the second XO and configuring the receiver of the wireless device to use the first XO or the second XO in accordance with the decision.

Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.