Abstract: A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M?2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N?1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak1) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme.

Abstract: Systems and methods are disclosed herein that relate to a wireless device that intelligently uses different reference crystal oscillators (XOs) for a Phase Locked Loop(s) (PLL(s)) in a transceiver of the wireless device. Embodiments of a method of operation of a wireless device comprising a first XO that operates at a first reference frequency and a second XO that operates at a second reference frequency that is greater than the first reference frequency are disclosed. In some embodiments, the method of operation of the wireless devices comprises making a decision as to whether to configure a receiver of the wireless device to use the first XO or the second XO and configuring the receiver of the wireless device to use the first XO or the second XO in accordance with the decision.

Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.

Abstract: A power amplifier arrangement comprises a power amplifier comprising at least one transistor having a first gate and a second gate. The first gate is configured to receive a radio frequency input signal superimposed with a first control signal, and the second gate is configured to receive a second control signal. The first control signal is a linearization signal varying in relation to an envelope of the input signal and the second control signal is a temperature compensation signal varying in relation to a temperature of the power amplifier, or vice versa.

Abstract: A receiver circuit for an antenna array system (AAS) is disclosed. The receiver circuit (10) comprises a set of receivers (151-15p). Each receiver (151-15p) comprises a first TI-ADC (351) in a receive path of the receiver. The first TI-ADC (351) comprises a plurality of sub ADCs (A1-AM+N). Each receiver (151-15p) comprises a control circuit (40) configured to select which sub ADC (A1-AM+N) is to operate on what input sample based on a first selection sequence. The control circuits (40) in the different receivers (151-15p) in said set of receivers (151-15p) are configured to use different first selection sequences.

Abstract: An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).

Abstract: A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M?2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N?1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak1) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme.

Abstract: A method of scheduling wireless data transmissions between a mobile terminal (701) and a base station using multiple component carrier signals is disclosed. The method comprises the steps of: receiving in the mobile terminal information from the base station indicating available component carriers; detecting in the mobile terminal at least one dynamic parameter indicative of the mobile terminal's current ability to handle component carriers having non-contiguous bandwidths; determining in the mobile terminal in dependence of the at least one dynamic parameter which of the available component carriers to utilize; and transmitting from the mobile terminal to the base station information indicating the component carriers determined to utilize.

Abstract: A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

Abstract: A method of a wireless transmitter is disclosed. The method is for mitigation of distortion caused by non-linear hardware components of the transmitter, wherein mitigation of distortion comprises mitigating at least one intermodulation component, wherein the transmitter is configured to process an input signal having an input signal spectrum, and wherein the transmitter comprises two or more signal branches, each signal branch comprising a respective non-linear hardware component. The method comprises modifying the input signal for a first one of the signal branches by applying a first phase shift to a first part of the input signal spectrum, wherein the first phase shift has a first sign and a first absolute value, and applying a second phase shift to a second part of the input signal spectrum. The second phase shift has a second sign which is opposite to the first sign, and a second absolute value which is equal to the first absolute value. The first and second parts are non-overlapping.

Abstract: A receiver circuit for an antenna array system (AAS) is disclosed. The receiver circuit (10) comprises a set of receivers (151-15p). Each receiver (151-15p) comprises a first TI-ADC (351) in a receive path of the receiver. The first TI-ADC (351) comprises a plurality of sub ADCs (A1-AM+N). Each receiver (151-15p) comprises a control circuit (40) configured to select which sub ADC (A1-AM+N) is to operate on what input sample based on a first selection sequence. The control circuits (40) in the different receivers (151-15p) in said set of receivers (151-15p) are configured to use different first selection sequences.

Abstract: A method of scheduling wireless data transmissions between a mobile terminal (701) and a base station using multiple component carrier signals is disclosed. The method comprises the steps of: receiving in the mobile terminal information from the base station indicating available component carriers; detecting in the mobile terminal at least one dynamic parameter indicative of the mobile terminal's current ability to handle component carriers having non-contiguous bandwidths; determining in the mobile terminal in dependence of the at least one dynamic parameter which of the available component carriers to utilize; and transmitting from the mobile terminal to the base station information indicating the component carriers determined to utilize.

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a set of transceivers comprising a plurality of transceivers, all configured to transmit in the same transmit frequency band and receive in the same receive frequency band. Furthermore, the integrated circuit has a set of frequency synthesizers including a separate frequency synthesizer associated with each transceiver in the set of transceivers, wherein each frequency synthesizer in the set is configured to generate a local-oscillator (LO) signal to its associated transceiver. Moreover, the integrated circuit includes a control circuit configured to control the set of frequency synthesizers such that nearest neighbors in the set of frequency synthesizers generate LO signals at different frequencies (f1, f2, f3, f4).

Abstract: Disclosed is a SAR ADC (Ai) having an input for receiving an input voltage, a comparator, a first switch network configured to be controlled by the SAR state machine and connected to the input of the SAR ADC and to reference voltage nodes, and a first capacitor network. The first capacitor network has a first node connected to an input of the comparator, a second node, and a bridge capacitor (Cb) connected between the first node and the second node. Furthermore, the first capacitor network comprises a first set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the first set is connected to the first node and the second terminal of each capacitor in the first set is connected to the switch network.

Abstract: An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).

Abstract: A network node and a wireless device for operation in a wireless communication network, wherein it is determined that a second scheduling bandwidth is needed, based on an amount or type of data buffered for transmission to the wireless device. Reconfiguration of a receiver bandwidth of the wireless device is initiated to match the second scheduling bandwidth, wherein the second scheduling bandwidth is larger than a first scheduling bandwidth currently associated with the wireless device, and wherein the rust and second scheduling bandwidths respectively define the bandwidth used for scheduling transmissions to the wireless device. Methods and computer programs therefor are also disclosed.

Abstract: A technique for generating a radio signal (504) for transmitting a protocol data unit (PDU) in a radio network is described. The PDU includes a first portion and a second portion. As to a method aspect of the technique, a first signal indicative of the first portion of the PDU is amplified for radio transmission using a power amplifier (630) in a first operating state. The power amplifier is switched from the first operating state to a second operating state different from the first operating state. A second signal indicative of the second portion of the PDU is amplified for radio transmission using the power amplifier in the second operating state, wherein a first bandwidth of the first signal is greater than a second bandwidth of the second signal.