Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Rework for metal interconnects using etch and thermal anneal
    Patent number: 10658235
    Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Prasad Bhosale, Terry A. Spooner, Chih-Chao Yang, Lawrence A. Clevenger
  • Selective ILD deposition for fully aligned via with airgap
    Patent number: 10651078
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 12, 2020
    Assignee: Tessera, Inc.
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • DIRECT BONDED HETEROGENEOUS INTEGRATION PACKAGING STRUCTURES
    Publication number: 20200144187
    Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
  • INTEGRATION OF ARTIFICIAL INTELLIGENCE DEVICES
    Publication number: 20200135635
    Abstract: Techniques that facilitate integration of artificial intelligence devices are provided. In one example, a device includes a first dual-damascene layer, a second dual-damascene layer and an artificial intelligence memory device. The first dual-damascene layer comprises a first set of copper connections formed in first dielectric material. The second dual-damascene layer that comprises a second set of copper connections formed in second dielectric material. The artificial intelligence memory device is integrated between the first dual-damascene layer and the second dual-damascene layer. A through-level via (TLV) electrical connection associated with the artificial intelligence memory device provides an interconnection between the first set of copper connections and the second set of copper connections.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Hsueh-Chung Chen, Lawrence A. Clevenger, Fee Li Lie, Effendi Leobandung
  • FULLY ALIGNED SEMICONDUCTOR DEVICE WITH A SKIP-LEVEL VIA
    Publication number: 20200136028
    Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 30, 2020
    Inventors: Nicholas A. Lanzillo, Benjamin D. Briggs, Chih-Chao Yang, Hsueh-Chung Chen, Lawrence A. Clevenger
  • METAL SPACER SELF ALIGNED DOUBLE PATTERNING WITH AIRGAP INTEGRATION
    Publication number: 20200135537
    Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Hsueh-Chung Chen, James Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • STRUCTURE AND METHOD FOR FORMING FULLY-ALIGNED TRENCH WITH AN UP-VIA INTEGRATION SCHEME
    Publication number: 20200135560
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive via extending vertically from a conductive layer, and depositing a first dielectric layer on the conductive layer and on lateral sides the conductive via. In the method, the conductive via is recessed with respect to a top surface of the first dielectric layer. An etch stop layer is deposited on the top surface of the first dielectric layer and on a top surface of the conductive via, and a second dielectric layer is deposited on the etch stop layer. The method also includes removing portions of the etch stop layer and the second dielectric layer to create a plurality of trenches spaced apart from each other. A trench of the plurality of trenches is formed over and exposes at least part of the conductive via, and a conductive material is deposited in the plurality of trenches.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Benjamin D. Briggs
  • Contacts having a geometry to reduce resistance
    Patent number: 10636738
    Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Dielectric Damage-Free Dual Damascene Cu Interconnects Without Barrier at Via Bottom
    Publication number: 20200126854
    Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Lawrence A. Clevenger
  • COGNITIVE SYSTEM FOR LOCALIZED LIDAR POLLUTION DETECTION USING AUTONOMOUS VEHICLES
    Publication number: 20200125969
    Abstract: The present invention provides for a cognitive system using an autonomous vehicle includes a plurality of sensors configured to obtain the weather forecast for a pollution detectable area; a cognitive input to determine the pollution detectable area having highest sensitivity of pollution; a light detecting and ranging system configured to spatially probe pollution levels distributed in the pollution detectable area; an evaluation system to evaluate the probed pollution levels in the pollution detectable area; and a recommendation system for recommending an action to be taken based on evaluation system results of the probed pollution levels in the pollution detectable area, wherein the pollution levels are detected based light emitted by the light detecting and ranging system.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo
  • Non-intrusive unmanned entity inspection
    Patent number: 10629009
    Abstract: An unmanned vehicle is identified. One or more specifications of the unmanned vehicle are retrieved in response to the identification. A first characteristic of the unmanned vehicle is observed. The observed first characteristic is compared to the retrieved specifications. A compliance standard of the unmanned vehicle is determined. The determination is based on the comparison.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yuk L. Chan, Eileen P. Tedesco, Kyle Gilbertson, Daniel F. Hogerty, Lawrence A. Clevenger, Benjamin D. Briggs
  • Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
    Patent number: 10629529
    Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 21, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Dual-damascene formation with dielectric spacer and thin liner
    Patent number: 10629478
    Abstract: A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a sacrificial dielectric layer and a first dielectric layer until a top portion of a first conductive material, the dielectric spacer includes a dielectric material having a dielectric constant higher than a dielectric constant of the sacrificial dielectric layer and higher than a dielectric constant of the first dielectric layer, conformally depositing a barrier liner within the plurality of interconnect openings above and in direct contact with the dielectric spacer, filling the interconnect openings with a second conductive material, removing the sacrificial dielectric layer to expose portions of the dielectric spacer above the first dielectric layer, and reducing a thickness of exposed portions of the dielectric spacer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Huai Huang, Christopher J. Penny, Michael Rizzolo, Hosadurga Shobha
  • METAL SPACER SELF ALIGNED MULTI-PATTERNING INTEGRATION
    Publication number: 20200118872
    Abstract: A method and structure of forming an interconnect structure with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 16, 2020
    Inventors: HSUEH-CHUNG CHEN, James J. Kelly, Yann MIGNOT, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Dielectric gap fill evaluation for integrated circuits
    Patent number: 10622250
    Abstract: Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Gauri Karve, Fee Li Lie, Nicole Adelle Saulnier, Indira Seshadri, Hosadurga Shobha
  • RESISTIVE MEMORY CROSSBAR ARRAY WITH RUTHENIUM PROTECTION LAYER
    Publication number: 20200111958
    Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including at least a hardmask having a first layer and a second layer, the second layer being a ruthenium layer, and removing the first layer of dual layer hardmask during a via opening such that the ruthenium layer remains intact to protect the RRAM stack during a damascene process.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Takashi Ando, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • RESISTIVE MEMORY DEVICE WITH MESHED ELECTRODES
    Publication number: 20200111837
    Abstract: A method is presented for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array. The method includes forming a conductive line within an interlayer dielectric (ILD), constructing a barrier layer over a portion of the conductive line, forming a bottom meshed electrode, depositing a dielectric layer over the bottom meshed electrode, and forming a top meshed electrode over the dielectric layer, where each of the top and bottom meshed electrodes includes a plurality of isolations films.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 9, 2020
    Inventors: Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang, Michael Rizzolo
  • RESISTIVE MEMORY DEVICE WITH MESHED ELECTRODES
    Publication number: 20200111838
    Abstract: A method is presented for incorporating a resistive random access memory (RRAM) stack within a resistive memory crossbar array. The method includes forming a conductive line within an interlayer dielectric (ILD), constructing a barrier layer over a portion of the conductive line, forming a bottom meshed electrode, depositing a dielectric layer over the bottom meshed electrode, and forming a top meshed electrode over the dielectric layer, where each of the top and bottom meshed electrodes includes a plurality of isolations films.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 9, 2020
    Inventors: Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang, Michael Rizzolo
  • Authentication of medication delivery vehicle to facilitate medication release
    Patent number: 10614918
    Abstract: A delivery device includes a circuit for receiving an authentication signal. The delivery device contains a substance encapsulated therein. The delivery device determines whether a user is authenticated based upon the authentication signal and an identifier stored within the delivery device. The delivery device heats, responsive to determining that the user is not authenticated within a predetermined time period after the delivery device being ingested by the user, the substance encapsulated within the delivery device.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ira L. Allen, Gregory J. Boss, Lawrence A. Clevenger, Andrew R. Jones, Kevin C. McConnell, John E. Moore, Jr.
  • Surface nitridation in metal interconnects
    Patent number: 10615116
    Abstract: A conductive interface includes a first conductor having a recessed area in least one surface. A dielectric layer has a trench positioned over the first conductor. A nitridized layer is formed on a top surface of the first conductor around the recessed area, to a depth on the first conductor that is shallower than a depth of the recessed area. A second conductor is formed in the trench and the recessed area to form a conductive contact with the first conductor.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang