Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS
    Publication number: 20200350211
    Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventors: Kangguo CHENG, Lawrence A. CLEVENGER, Balasubramanian S. PRANATHARTHIHARAN, John ZHANG
  • Metal spacer self aligned multi-patterning integration
    Patent number: 10825726
    Abstract: A method and structure of forming an interconnect structure with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions
    Patent number: 10818751
    Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger
  • TOP VIA PROCESS ACCOUNTING FOR MISALIGNMENT BY INCREASING RELIABILITY
    Publication number: 20200335393
    Abstract: A method for fabricating a semiconductor device to account for misalignment includes forming a top via on a first conductive line formed on a substrate, forming liners each using a first dielectric material, including forming first and second liners to a first height along sidewalls of the top via, forming dielectric layers, including forming first and second dielectric layers on the first conductive line to the first height and adjacent to the first and second liners, respectively, recessing the top via to a second height, and forming an additional dielectric layer on the recessed top via to the first height using a second dielectric material. The first and second dielectric materials are selected to compensate for potential misalignment between the first conductive line and the top via.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Inventors: Chen Zhang, Lawrence A. Clevenger, Benjamin D. Briggs, Brent A. Anderson, Chih-Chao Yang
  • Metal spacer self aligned double patterning with airgap integration
    Patent number: 10811310
    Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size
    Patent number: 10811599
    Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Liying Jiang, Sebastian Naczas, Michael Rizzolo, Chih-Chao Yang
  • Auto-incorrect in chatbot human-machine interfaces
    Patent number: 10812417
    Abstract: Context appropriate errors are injected into conversational text generated by conversational agents. The conversational agent creates an imperfect conversational text containing at least one text entry error added to the original conversational text. A confidence level that at least one of context and meaning of the imperfect conversational text is consistent with the context and meaning of the original conversational text is determined, and the imperfect conversational text is communicated to a human recipient if the confidence level is above a pre-defined threshold.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christoper J. Penny, Michael Rizzolo, Aldis Sipolins
  • DOUBLE METAL PATTERNING
    Publication number: 20200328111
    Abstract: A technique relates to a semiconductor device. Mandrels are formed on a substrate, the mandrels including a first metal layer. A second metal layer is formed on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Inventors: HSUEH-CHUNG CHEN, YONGAN Xu, Yann MIGNOT, James Kelly, Lawrence A. Clevenger
  • Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
    Patent number: 10804204
    Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joshua Rubin, Lawrence A. Clevenger, Charles L. Arvin
  • Magnetic tunnel junction with low series resistance
    Patent number: 10796833
    Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas A. Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert, Lawrence A. Clevenger, James Stathis
  • Protuberant contacts for resistive switching devices
    Patent number: 10790445
    Abstract: Embodiments of the invention are directed to a resistive switching device (RSD) that includes a first terminal, a second terminal, an active region having a switchable conduction state, and a protuberant contact communicatively coupled to the first terminal. The protuberant contact is configured to communicatively couple the first terminal through a first barrier liner to a first electrode line of a crossbar array. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not impacting the switchable conduction state of the active region. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not directly contact the first terminal.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: September 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Chih-Chao Yang, Lawrence A. Clevenger
  • COGNITIVE SYSTEM FOR AUTOMATIC RISK ASSESSMENT, SOLUTION IDENTIFICATION, AND ACTION ENABLEMENT
    Publication number: 20200302352
    Abstract: A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Alex Richard Hubbard, Spyridon Skordas, Marc A. Bergendahl, Cody John Murray, Gauri Karve, Lawrence A. Clevenger
  • SEMICONDUCTOR DEVICE WITH SELECTIVE INSULATOR FOR IMPROVED CAPACITANCE
    Publication number: 20200303239
    Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include an alternating arrangement of vertical metallic lines defining openings therebetween on a substrate. An interlevel dielectric layer is disposed on a consecutive first opening and a second opening to seal an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Michael Rizzolo, Lawrence A. Clevenger, Huai Huang, Hosadurga Shobha
  • Self-aligned airgaps with conductive lines and vias
    Patent number: 10784156
    Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Semiconductor device and method of forming the semiconductor device
    Patent number: 10784159
    Abstract: A semiconductor device includes a first dielectric layer including a first contact hole, a second dielectric layer formed on the first dielectric layer, and including a second contact hole aligned with the first contact hole, and a reflowed copper layer formed in the first and second contact holes.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
  • Binaural audio calibration
    Patent number: 10785590
    Abstract: A computer-implemented method for calibrating audio of a virtual reality device, the method comprising: determining a difference between a perceived tone location and an actual audible tone location, in response to an emitting of the actual audible tone; wherein the tone comprises a spectral tone, and creating and calibrating a user ear model by: emitting the spectral tone at a random time during a simulation by the virtual reality device; determining the perceived tone location during the simulation; and computing an error adjustment for one or more geometric variables of a default ear model based on a result of the determining.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Leigh Anne Hodges Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Gunars Sipolins
  • Method and structure to construct cylindrical interconnects to reduce resistance
    Patent number: 10784197
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha
  • FORMING A BACKSIDE GROUND OR POWER PLANE IN A STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR
    Publication number: 20200286793
    Abstract: Techniques facilitating forming a backside ground or power plane in stacked vertical transport field effect transistor are provided. A semiconductor structure can comprise a first field effect transistor (FET). The semiconductor structure can also comprise a second FET. The first FET can be vertically stacked on a first surface of the second FET. The second FET can be electrically coupled to a conductive plane on a second surface of the second FET, the second surface being opposite to the first surface.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventors: Chen Zhang, Tenko Yamashita, Kangguo Cheng, Lawrence A. Clevenger
  • THREE-DIMENSIONAL AND PLANAR MEMORY DEVICE CO-INTEGRATION
    Publication number: 20200286956
    Abstract: A method for fabricating a semiconductor device including three-dimensional and planar memory device co-integration includes forming trenches within a horizontal electrode stack to expose portions of a conductive layer, forming vertical electrodes including conductive material within the trenches, forming a planar memory device stack across the device, and patterning the planar memory device stack to form a planar memory device.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Takashi Ando, Michael Rizzolo, Chih-Chao Yang, Lawrence A. Clevenger
  • Location-specific laser annealing to improve interconnect microstructure
    Patent number: 10770348
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Michael Rizzolo