Patents by Inventor Lawrence S. Mok

Lawrence S. Mok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8667049
    Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Dong Chen, George L. Chiu, Thomas M. Cipolla, Paul W. Coteus, Alan G. Gara, Mark E. Giampap, Philip Heidlberger, Gerard V. Kopcsay, Lawrence S. Mok, Todd E. Takken
  • Publication number: 20120328789
    Abstract: A method of producing a metal-graphite foam composite, and particularly, the utilization thereof in connection with a cooling apparatus. Also provided is a cooling apparatus, such as a liquid cooler or alternatively, a heat sink for electronic heat-generating components, which employ the metal-graphite foam composite.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Minhua Lu, Lawrence S. Mok, Krystyna W. Semkow
  • Publication number: 20120311299
    Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.
    Type: Application
    Filed: August 3, 2012
    Publication date: December 6, 2012
    Applicant: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Dong Chen, George L. Chiu, Thomas M. Cipolla, Paul W. Coteus, Alan G. Gara, Mark E. Giampapa, Philip Heidlberger, Gerard V. Kopcsay, Lawrence S. Mok, Todd E. Takken
  • Patent number: 8250133
    Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System- On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Dong Chen, George L. Chiu, Thomas M. Cipolla, Paul W. Coteus, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Gerard V. Kopcsay, Lawrence S. Mok, Todd E. Takken
  • Publication number: 20120170221
    Abstract: An arrangement for improving the cooling efficiency of semiconductor chips. One embodiment is to construct a vapor chamber with one compliant surface for improving the efficiency of transferring heat from a semiconductor chip to the vapor chamber, and another embodiment is to construct a vapor chamber with the chip substrate such that the chips are embedded inside the vapor chamber. One surface of the vapor chamber has a flexible structure to enable the surface of the vapor chamber to be compliant with the surface of a chip or a heat sink device.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lawrence S. Mok
  • Patent number: 8176972
    Abstract: An arrangement for improving the cooling efficiency of semiconductor chips. One embodiment is to construct a vapor chamber with one compliant surface for improving the efficiency of transferring heat from a semiconductor chip to the vapor chamber, and another embodiment is to construct a vapor chamber with the chip substrate such that the chips are embedded inside the vapor chamber. One surface of the vapor chamber has a flexible structure to enable the surface of the vapor chamber to be compliant with the surface of a chip or a heat sink device.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventor: Lawrence S. Mok
  • Patent number: 8138085
    Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
  • Patent number: 8110746
    Abstract: A structure. The structure includes an interposer adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Minhua Lu, Lawrence S. Mok
  • Patent number: 8059400
    Abstract: A method of forming a structure. An interposer is provided. The interposer is adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Minhua Lu, Lawrence S. Mok
  • Publication number: 20110201199
    Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.
    Type: Application
    Filed: April 25, 2011
    Publication date: August 18, 2011
    Applicant: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
  • Patent number: 7948077
    Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: May 24, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Evan G. Colgan, Lawrence S. Mok, Chirag S. Patel, David E. Seeger
  • Patent number: 7947599
    Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: May 24, 2011
    Assignee: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
  • Patent number: 7888786
    Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Evan G. Colgan, Lawrence S. Mok, Chirag S. Patel, David E. Seeger
  • Patent number: 7888603
    Abstract: A structure. The structure includes a substrate and an interposer. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N?2). The interposer includes N continuous interposer channels coupled to the N substrate channels to form M continuous loops (1?M?N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Minhua Lu, Lawrence S. Mok
  • Patent number: 7856711
    Abstract: A method of forming structure. A substrate and an interposer are provided. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N?2). N interposer channels are coupled to the N substrate channels so as to form M continuous loops (1?M?N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Minhua Lu, Lawrence S. Mok
  • Patent number: 7836314
    Abstract: A method, system and computer readable medium for maximizing the performance of a computer system that includes at least one computing unit. Temperature and location data for each computing unit is received by a server unit and the location of each computing unit within a given environment is reevaluated and revised to maximize the overall performance of the computer system.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Trieu C. Chieu, Hoi Y. Chan, Vinod Kamath, Lawrence S. Mok
  • Publication number: 20100117209
    Abstract: The present invention is directed to a method of packaging multiple semiconductor chips on a second semiconductor chips with a built-in efficient cooling means. One embodiment is to place two multiple chip stacks on opposing sides of a vapor chamber for transferring heat away from the semiconductor chips. Another embodiment is to construct a vapor chamber with a substrate such that at least one multiple chip stack is embedded inside the vapor chamber.
    Type: Application
    Filed: February 28, 2007
    Publication date: May 13, 2010
    Inventors: Raschid J. Bezama, Minhua Lu, Lawrence S. Mok
  • Publication number: 20090259713
    Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.
    Type: Application
    Filed: June 26, 2009
    Publication date: October 15, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthias A. Blumrich, Dong Chen, George L. Chiu, Thomas M. Cipolla, Paul W. Coteus, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Gerard V. Kopcsay, Lawrence S. Mok, Todd E. Takken
  • Patent number: 7570179
    Abstract: A wireless key is signal, having a key-specific identifier, is received, the key-specific identifier detected, and the signal transmission location is calculated. The signal transmission location is stored based on the detected key-specific identifier. Another instance of the same wireless key signal is received, its key-specific identifier is detected, and the stored signal transmission location is retrieved based on the detected key-specific identifier. Optionally, a wireless key signal is received at a user and repeated at a plurality of locations in a parking facility. A vehicle response is detected, and associated with one of the repeatings of the wireless key signal. A location of the vehicle response is detected based on the repeating with which it is associated.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: August 4, 2009
    Assignee: International Business Machines Corporation
    Inventors: Trieu C. Chieu, David L. Cohn, Shiwa S. Fu, Santhosh Kumaran, Lawrence S. Mok
  • Patent number: 7571461
    Abstract: A Method and system are disclosed for accessing personal Web site or executing electronic commerce with security in a smart Java card. A personal Web site which includes personal or private information is stored in a personal smart Java card. Before a user can access the Web site stored in the smart Java card, the user is validated by any one of or in combination of PIN, facial images, hand images, eye image, voice characteristics, and finger prints. In addition, an encryption engine embedded in the smart Java card decodes and compares the entered PIN combined with a secure key or security certificate to verify the identity of the user. Before the bank account can be accessed freely by the user, the bank's computer system checks the combined secure data to ensure the authenticity of the card and the user's identity with multiple check points using Internet security protocols via Web browsers.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 4, 2009
    Assignee: International Business Machines Corporation
    Inventors: Thomas Y. Kwok, Lawrence S. Mok