Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.

Abstract: Embodiments of the disclosure include a method for data mining shape based data, the method includes receiving shape data for each of a plurality of data entries and creating a first abstract from the shape data for each of the plurality of data entries. The method also includes organizing the first abstracts into a plurality of groups based on a criterion and creating a second abstract for each data entry in the plurality of groups based on the criterion and information derived from the first abstract.

Abstract: Embodiments of the disclosure include a method for data mining shape based data, the method includes receiving shape data for each of a plurality of data entries and creating a first abstract from the shape data for each of the plurality of data entries. The method also includes organizing the first abstracts into a plurality of groups based on a criterion and creating a second abstract for each data entry in the plurality of groups based on the criterion and information derived from the first abstract.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.

Abstract: Embodiments of the disclosure include a method for data mining shape based data, the method includes receiving shape data for each of a plurality of data entries and creating a first abstract from the shape data for each of the plurality of data entries. The method also includes organizing the first abstracts into a plurality of groups based on a criterion and creating a second abstract for each data entry in the plurality of groups based on the criterion and information derived from the first abstract.

Abstract: Embodiments of the disclosure include a method for data mining shape based data, the method includes receiving shape data for each of a plurality of data entries and creating a first abstract from the shape data for each of the plurality of data entries. The method also includes organizing the first abstracts into a plurality of groups based on a criterion and creating a second abstract for each data entry in the plurality of groups based on the criterion and information derived from the first abstract.

Abstract: Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

Abstract: A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.

Abstract: Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

Abstract: A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.

Abstract: A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.

Abstract: A structure and method for optimzing scan chain fail disgnosis. First, logic paths from target latches in a target scan chain to observation latches in at least one other observation scan chain are identified. Then, the locations of the observation latches within the other scan chains are optimized.

Abstract: Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

Abstract: A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.

Abstract: Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

Abstract: Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.

Abstract: A structure and method for performing scan chain diagnosis. The structure comprises a diagnosed/target scan chain and one or more good observation scan chains. Observing logic paths from the target scan chain to observation scan chains can be identified according to a pre-specified criterion. The diagnosed scan chain is loaded in series with a test pattern. Then, the contents of the observed latch(es) in the diagnosed scan chain propagate through the observing logic paths. Then, the output signals of the observing logic paths are strobed into the observing latch(es) in the observing scan chain(s). Then, the observing scan chain(s) are unloaded and the contents of the observing latch(es) are collected and analyzed to determine the defect types and the defect ranges in the diagnosed scan chain.

Abstract: The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

Abstract: A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.