INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION
A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
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1. Field of the Invention
The present invention generally relates to improving integrated circuit logic diagnostics by modeling physical layout information in the models used for diagnostic simulation and defect localization. An embodiment of the invention uses net connectivity information from integrated circuit layout to improve logic diagnostics and a heuristic method for determining when to include faults associated with clock or control signals in the fault candidate set for diagnostics.
2. Description of the Related Art
Modeling for test generation and diagnostic simulation uses logical test models, which model circuit logic and logical connectivity. Electrical behavior is typically modeled by stuck-at faults, transition faults or by adding patterns faults. Layout information may be indirectly included in the test netlist by customizing faults for a particular circuit. A physical defect mechanism can be mapped to electrical or logical behavior using default struck-at faults, pattern faults or composite faults. For example, mux circuits are often modeled by a mux primitive plus some pattern faults to get full coverage of the fail space for the circuit.
Gatemaker™ is an internal IBM® EDA tool. It may be used to create a gate level model directly from the layout to get accurate transistor level connections. Gatemaker™ improves the model to layout correspondence by better modeling the logic implementation. However, none of these methods include net structure in the model.
Diagnostics simulation, e.g., Cadence™ Encounter Test™, identifies a group of candidate faults that might explain the fail data from the chip being diagnosed. Test patterns are simulated for each fault and the resulting score is used to identify the faults most likely to explain the fail data. In the situation seen in
Commercial diagnostics tools, (like the Cadence™ Encounter Test™), calculate scores for each fault candidate based on how many failing and passing measures are explained, or not explained by the particular fault. In the above example referring to
In view of the foregoing and other exemplary problems, drawbacks, and disadvantages of the conventional methods and structures, an exemplary embodiment provides a computer-implemented method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout that identifies, by a computing device, failing observation points in an IC layout. Failing observation point's proximity geometry is determined in the IC circuit layout, and if proximity criteria for the failing observation points are determined to be satisfied, faults associated with the failing observation points that meet the proximity criteria are determined. The identified faults are then included in a fault candidate set.
Another exemplary embodiment provides a computer-implemented method that determines, by a computing device, net connectivity of a circuit using layout extraction. A buffer insertion point is determined based on the net connectivity, and a buffer model is inserted at the buffer insertion point in a test netlist. A fault model is updated based on the test netlist with the inserted buffer model.
Another exemplary embodiment of the invention provides a computer-implemented method including performing, by a computing device, a conetrace on a logic test netlist of an Integrated Circuit (IC) with fail data to identify one of fail faults, nets and instances within the circuit. Net connectivity is determined of the fail candidates using layout extraction, where a buffer insertion point is determined within the circuit based on the net connectivity. A buffer model is inserted at the buffer insertion point in the test netlist, and a fault model is updated based on the test netlist. Finally, a diagnostic result is output based on a diagnostic simulation of the updated fault model.
With these novel features, the embodiments of the invention use the novel concept of adding physical information by adding logic elements to the netlist, rather than creating pattern faults or changing the simulator. This has the advantages of not requiring any enhancements to general purpose simulators or creation of specialized pattern faults, yet provides a precise fault callout.
The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which:
Referring now to the drawings, and more particularly to
The semiconductor industry has a growing reliance on diagnostics and defect localization to provide feedback to manufacturing for yield learning. Functional analysis directed by diagnostics produces defect root causes linked to the electrical test failure.
Diagnostics is used to determine possible defect locations in ICs. Volume diagnostics produces diagnostics results from a large number of chips and is used in several ways: 1) diagnostics data analysis, i.e., failure analysis root cause determination; 2) design or system debug; 3) random defect directed FA and pareto generation for fabrication feedback; and 4) logic mapping, by overlaying PLY inspection data and diagnostics results. The number of nets and circuits called out and the accuracy of the diagnostics callout may be compromised for computing speed in volume diagnostics. Improved diagnostics may enable different trade-offs between speed, accuracy, and number of chips diagnosed and ultimately improve yield learning.
Volume diagnostics software applications are available to support routine uses above. These applications output diagnostics results from many chips at a time. Generally, speed and throughput are balanced with accuracy in setting up volume diagnostics. The routine uses of volume diagnostics are not usually compromised by this trade-off. Volume diagnostics results may be supplemented with more careful or complete diagnostics if necessary. Volume diagnostics allows a choice between many chips for FA submissions, and chips with sufficient diagnostic callouts may be selected.
As volume diagnostics becomes more readily available, more uses for volume diagnostics results are evolving, which may have different diagnostics quality requirements than in the past. Also, semi-conductor design and fabrication technology continue to evolve. Trade-offs that were reasonable in the past are starting to limit which failing chips complete diagnostics, which in turn, could limit which problems are represented in the diagnostics results.
For example, setting a maximum number of faults to process during diagnostics prevents diagnosing chips that have more fault candidates than the limit. In a design dependent world, this could translate to filtering out the chips that fail a certain type of macro or logic formation. The size of this sample may become proportionally larger depending on chip design styles and technology implementation guidelines.
Another example is setting diagnostics to exclude clock faults. There are often substantial faults associated with clock and select or enable signal trees. To minimize processing times, fault selection for diagnostics may be limited to faults in the backcones of observation latch functional data ports. One consequence of filtering out clock or global control signal faults is poor diagnostic results for particular chips, which have defects in the excluded circuitry. Another consequence might be poor representation in the pool of well diagnosed chips of defects on particular levels or with specific physical structures associated with clock or global control signal trees.
The embodiments of the invention model physical information by adding logic elements to the netlist and/or using layout based criteria to select candidate faults for diagnostic simulation. The embodiments of the invention do not require changing or creating new pattern faults, although the embodiments of the invention could accommodate both. This has the advantages of not requiring any enhancements to general purpose simulators or creation of specialized pattern faults, yet provides a precise fault callout.
Exemplary AspectsReferring again to the drawings,
Given the layout data 108, net connectivity is determined 106, using layout extraction. This layout extraction is explained in more detail in
A test netlist 116 is updated 114 by adding buffers at insertion points representing physical net branch points, and thereafter a fault model 118 may be updated 120, as necessary to include faults associated with net physical layout. Diagnostics simulation 124 may be performed with the updated test netlist 116 and the updated fault model 122.
Diagnostic results/callout 126 may be interpreted 128 in terms of net connectivity, when they include faults associated with inserted buffers and thus modified nets. This step may not be necessary depending on the end use of the diagnostic results. Finally, a diagnostic result 130 is produced and output.
Connectivity graph 600 includes a driver D, and a sink S connected to an intermediate node B, and an intermediate node A connected to intermediate node B, and two sinks S.
Thus, the embodiment of the invention models physical information in the layout. Net branch points are modeled by adding logic elements, (i.e., buffers), to the netlist at buffer insertion points. This embodiment of the invention may also be embodied as: 1) creating a full or partial dictionary for an integrated circuit combining steps 106 and 110 in
Determining the buffer insertion point, as illustrated in
Determining net connectivity of a circuit using layout extraction may further include building, by a computing device, a connectivity network of the circuit as a graph.
Determining net connectivity of a circuit using layout extraction further includes simplifying the graph, by a computing device.
Models for global nets including clock and/or control signal nets may be updated to reflect physical net connectivity as described previously.
Additionally, faults associated with shorts to power or ground might also be included based on a proximity measurement or lookup to power bussing.
The method of determining the physical proximity geometry may further include calculating a boundary around which the all failing observation points are included within, or calculating a predetermined physical distance between latches, or grouping failing observation points based on location in the layout and applying the proximity criteria to each group separately.
The embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment including both hardware and software elements. One embodiment of the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.
Furthermore, the embodiments of the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD.
A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
Input/output (I/O) devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.
A representative hardware environment for practicing the embodiments of the invention is depicted in
It should be understood that the corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. Additionally, it should be understood that the above-description of the embodiments of the invention have been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments of the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments of the present invention. The embodiments were chosen and described in order to best explain the principles of the embodiments of the invention and the practical application, and to enable others of ordinary skill in the art to understand the embodiments of the invention for various embodiments with various modifications as are suited to the particular use contemplated. Well-known components and processing techniques are omitted in the above-description so as to not unnecessarily obscure the embodiments of the invention.
Finally, it should also be understood that the terminology used in the above-description is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the invention. For example, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprises”, “comprising,” and/or “incorporating” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Claims
1. A computer-implemented method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC), said method comprising:
- identifying, by a computing device, failing observation points in an IC layout;
- determining, by said computing device, said failing observation points proximity geometry in said IC circuit layout;
- determining, by said computing device, if a proximity criteria for said failing observation points is met; and
- identifying, by said computing device, faults associated with said failing observation points that meet said proximity criteria; and
- including, by said computing device, said identified faults in a fault candidate set.
2. The method according to claim 1, wherein said determining said proximity geometry further includes:
- calculating, by said computing device, a boundary around which said failing observation points are included within.
3. The method according to claim 1, wherein said determining said proximity geometry further includes:
- calculating, by said computing device, calculating physical distances between said failing observation points.
4. The method according to claim 1, further comprising:
- identifying, by said computing device, faults in said logical model/test netlist associated with said failing observation points and including them in said fault candidate set.
5. The method according to claim 1, further comprising:
- updating, by said computing device, one of a logic model and a test netlist to model physical net connectivity of nets associated with said failing observation points.
6. The method according to claim 5, wherein said faults based on said IC layout information comprises faults associated with one of a clock signal, a control circuit signal and a circuit.
7. The method according to claim 1, further comprising:
- identifying, by said computing device, failing observation points associated with a common signal.
8. The method according to claim 1, wherein said determining said proximity geometry further includes:
- retrieving, by said computing device, failing observation point locations from one of a cross-reference lookup and a dictionary.
9. A computer-implemented method comprising:
- determining, by a computing device, net connectivity of a circuit using layout extraction;
- determining, by said computing device, a buffer insertion point based on said net connectivity;
- inserting, by said computing device, a buffer model at said buffer insertion point in a test netlist; and,
- updating, by said computing device, a fault model based on said test netlist with said inserted buffer model.
10. The method according to claim 9, where said determining said buffer insertion point further comprises:
- starting at one of a net source and a driver, identifying, by said computing device, a first downstream net branch point.
11. The method according to claim 10, where said determining said buffer insertion point further comprises:
- determining, by said computing device, if the first downstream net branch point contains more than one fanout and determining a buffer insertion point at each downstream branch with more than one fanout.
12. The method according to claim 11, where said determining said buffer insertion point further comprises:
- starting at said buffer insertion point, identifying, by a computing device, another downstream net branch point.
13. The method according to claim 12, where said determining said buffer insertion point further comprises:
- determining, by a computing device, that the other downstream net branch point contains more than one fanout.
14. The method according to claim 13, where said determining said buffer insertion point further comprises:
- determining, by a computing device, a buffer insertion point at each downstream branch with more than one fanout.
15. The method according to claim 9, wherein said determining said net connectivity of said circuit using layout extraction further includes:
- building, by said computing device, a connectivity network of the circuit as a graph.
16. A computer-implemented method comprising:
- performing, by a computing device, a conetrace on a logic test netlist of an Integrated Circuit (IC) with fail data to identify one of fail faults, nets and instances within said circuit;
- determining, by said computing device, net connectivity of said fail candidates using layout extraction;
- determining, by said computing device, a buffer insertion point within said circuit based on said net connectivity;
- inserting, by said computing device, a buffer model at said buffer insertion point in said test netlist;
- updating, by said computing device, an updated fault model based on said test netlist; and
- outputting, by said computing device, a diagnostic result based on a diagnostic simulation of said updated fault model.
17. The method according to claim 16, wherein said determining said buffer insertion point further comprises:
- starting at a net source/driver, identifying, by said computing device, a first downstream net branch point.
- determining, by said computing device, if said first downstream net branch point contains more than one fanout; and
- determining, said buffer insertion point at each downstream branch with more than one fanout.
18. The method according to claim 16, wherein said determining said buffer insertion point further comprises:
- starting at said inserted buffer insertion point, identify, by said computing device, another downstream net branch point;
- determining, by said computing device, if said another downstream net branch point contains more than one fanout; and
- determining, said buffer insertion point at each downstream branch with more than one fanout.
19. The method according to claim 16, wherein said determining net connectivity of a circuit using layout extraction further comprises:
- building, by said computing device, a connectivity network of said circuit as a graph.
20. The method according to claim 19, wherein nodes represent layout segments, including net drivers and sinks, and lines represent connections between nodes, and
- wherein each said inserted buffer is associated with said layout segments.
21. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC), said method comprising:
- identifying, by a computing device, failing observation points in an IC layout;
- determining, by said computing device, said failing observation points proximity geometry in said IC circuit layout;
- determining, by said computing device, if a proximity criteria for said failing observation points is met; and
- identifying, by said computing device, faults associated with said failing observation points that meet said proximity criteria; and
- including, by said computing device, said identified faults in a fault candidate set.
22. A program storage device according to claim 21, wherein said determining said proximity geometry further includes:
- calculating, by said computing device, a boundary around which said failing observation points are included within.
23. A program storage device according to claim 21, wherein said determining said proximity geometry further includes:
- calculating, by said computing device, calculating physical distances between said failing observation points.
24. A program storage device according to claim 21, further comprising:
- identifying, by said computing device, faults in said logical model/test netlist associated with said failing observation points and including them in said fault candidate set.
25. A program storage device according to claim 21, further comprising:
- updating, by said computing device, one of a logic model and a test netlist to model physical net connectivity of nets associated with said failing observation points.
Type: Application
Filed: Dec 8, 2009
Publication Date: Jun 9, 2011
Patent Grant number: 8566059
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Rao H. Desineni (Essex Junction, VT), Maroun Kassab (Essex Junction, VT), Mary P. Kusko (Poughkeepsie, NY), Leah M. Pastel (Essex Junction, VT)
Application Number: 12/633,151
International Classification: G01R 31/14 (20060101); G06F 17/50 (20060101);