Patents by Inventor Lei Bi

Lei Bi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7995893
    Abstract: A magneto-optical structure is provided. The magneto-optical structure includes a substrate. A waveguide layer is formed on the substrate for guiding electromagnetic radiation received by the magneto-optical structure. The waveguide layer includes magnetic oxide material that comprises ABO3 perovskite doped with transition metal ions on the B site, or transition metal ions doped SnO2, or transition metal ions doped CeO2.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: August 9, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Lei Bi, Gerald F. Dionne, Hyun Suk Kim, Caroline A. Ross
  • Publication number: 20100238536
    Abstract: A magneto-optical isolator device is provided. The isolator device includes a substrate and a bottom cladding layer that is formed on the substrate. An optical resonator structure is formed on the bottom cladding layer. The resonator structure includes crystalline or amorphous diamagnetic silicon or silicon-germanium so as to provide non-reciprocal optical isolation. A top cladding layer is formed on the resonator structure. One or more magnetic layers positioned on the top cladding layer or between the top cladding or bottom cladding layers and the optical resonator structure.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 23, 2010
    Inventors: Juejun Hu, Lei Bi, Lionel C. Kimerling, Gerald F. Dionne, Caroline A. Ross
  • Publication number: 20100011043
    Abstract: A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.
    Type: Application
    Filed: April 11, 2006
    Publication date: January 14, 2010
    Applicant: NXP B.V.
    Inventors: Tianya Pu, Lei Bi, Jerome Tjia
  • Publication number: 20090213981
    Abstract: A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the registers and configured to receive input data and selectively deliver the input data to the registers. A data output circuit (340) is coupled to the data registers and configured to selectively output the output data. A selector (350) is coupled to the data input circuit and the data output circuit, and configured to permit the input data it enter selected registers through the data input circuit and permit selected registers to output data through the data output circuit. The invention provides an efficient technique for loading the shift registers without a large number of simultaneous serial shifts. The result is a power-efficient that achieves high performance objectives while minimizing power consumption.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 27, 2009
    Applicant: NXP B.V.
    Inventors: Lei Bi, Tianyan Pu
  • Publication number: 20090136191
    Abstract: A magneto-optical structure is provided. The magneto-optical structure includes a substrate. A waveguide layer is formed on the substrate for guiding electromagnetic radiation received by the magneto-optical structure. The waveguide layer includes magnetic oxide material that comprises ABO3 perovskite doped with transition metal ions on the B site, or transition metal ions doped SnO2, or transition metal ions doped CeO2.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 28, 2009
    Inventors: Lei Bi, Gerald F. Dionne, Hyun Suk Kim, Caroline A. Ross
  • Publication number: 20090070394
    Abstract: A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value.
    Type: Application
    Filed: March 23, 2006
    Publication date: March 12, 2009
    Applicant: NXP B.V.
    Inventors: Tianyan Pu, Lei Bi
  • Patent number: 7079467
    Abstract: A data processing apparatus having a partial response forward equalizer (filter) with sufficient number of taps to result in 7-tap target response, designed by jointly optimizing the target response and the target coefficients to maximize an appropriate signal-to-noise ratio (SNR) at the detector input, followed by a new post-processing scheme enhances performance of the threshold based bit-by-bit detector designed for the d=2 optical channels. The resulting performance of the proposed scheme over a range of channel densities of 4.5 and below (used on EFM/EFMPlus coded channels for CD/DVD), is close to maximum-likelihood bound (MLB), and it is better than that of other schemes at channel densities of 4.5 and higher. Advantageously, the detector of the invention is simple in structure compared to conventional partial response Viterbi detector schemes. By processing the detected data in accordance with a set of data correction rules, the invention provides advantageous enhanced detection capacity.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: July 18, 2006
    Assignee: Data Storage Institute
    Inventors: Kalahasthi Chenchu Indukumar, Lei Bi
  • Publication number: 20020114247
    Abstract: A data processing apparatus having a partial response forward equalizer (filter) with sufficient number of taps to result in 7-tap target response, designed by jointly optimizing the target response and the target coefficients to maximize an appropriate signal-to-noise ratio (SNR) at the detector input, followed by a new post-processing scheme enhances performance of the threshold based bit-by-bit detector designed for the d=2 optical channels. The resulting performance of the proposed scheme over a range of channel densities of 4.5 and below (used on EFM/EFMPlus coded channels for CD/DVD), is close to maximum-likelihood bound (MLB), and it is better than that of other schemes at channel densities of 4.5 and higher. Advantageously, the detector of the invention is simple in structure compared to conventional partial response Viterbi detector schemes. By processing the detected data in accordance with a set of data correction rules, the invention provides advantageous enhanced detection capacity.
    Type: Application
    Filed: August 28, 2001
    Publication date: August 22, 2002
    Inventors: Kalahasthi Chenchu Indukumar, Lei Bi