Patents by Inventor Lei Wan

Lei Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12674534
    Abstract: A fluid connector includes a second pin accommodated in a first pin. Prior to mating of the fluid connector and a complementary connector, a front end of the first pin protrudes forward out of the pin hole, the second pin is located within the pin hole, and a front end of the second pin is accommodated in the accommodating slot. When the fluid connector is mated with the complementary connector, the complementary connector abuts against the first pin, such that the first pin moves backward within the pin hole, and the front end of the second pin moves forward until it is accommodated in the complementary connector. The first pin and the second pin share the same pin hole, and the second pin occupies at least a portion of the inner space of the first pin, thereby facilitating saving the space of the shell.
    Type: Grant
    Filed: January 16, 2025
    Date of Patent: July 7, 2026
    Assignee: LOTES CO., LTD
    Inventors: Lei Wan, Chih-Kun Chen, Wen-Cong Zhang
  • Publication number: 20260173000
    Abstract: A short-range communication method includes that a first node receives at least one piece of node information from at least one node; and the first node controls the first node to establish time-frequency synchronization with a second node that is in the at least one node and that belongs to a second synchronization area, where node information from the second node includes synchronization information of the second synchronization area, and the synchronization information indicates at least one of a node identifier, a synchronization status, or a synchronization direction between nodes in the second synchronization area.
    Type: Application
    Filed: February 9, 2026
    Publication date: June 18, 2026
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xingqing Cheng, Lei Gao, Lei Wan, Changqing Yang, Jian Wang
  • Publication number: 20260166100
    Abstract: A Lactiplantibacillus plantarum subsp. plantarum strain, and a bacterial membrane vesicles derived from Lactiplantibacillus plantarum subsp. plantarum strain, and uses of the same for improvement of eye diseases are provided. The Lactiplantibacillus plantarum subsp. plantarum strain EP21 and the bacterial membrane vesicles are derived from Lactiplantibacillus plantarum subsp. plantarum strain EP21. Both the Lactiplantibacillus plantarum subsp. plantarum strain EP21 and the bacterial membrane vesicles derived from Lactiplantibacillus plantarum subsp. plantarum strain EP21 can inhibit inflammation by suppressing inflammatory factors and improve eye diseases effectively.
    Type: Application
    Filed: December 12, 2024
    Publication date: June 18, 2026
    Inventors: Lei Wan, Hui-Ju Lin, Yu-An Hsu, Chi-Fong Lin
  • Publication number: 20260078852
    Abstract: A fluid connector includes a second pin accommodated in a first pin. Prior to mating of the fluid connector and a complementary connector, a front end of the first pin protrudes forward out of the pin hole, the second pin is located within the pin hole, and a front end of the second pin is accommodated in the accommodating slot. When the fluid connector is mated with the complementary connector, the complementary connector abuts against the first pin, such that the first pin moves backward within the pin hole, and the front end of the second pin moves forward until it is accommodated in the complementary connector. The first pin and the second pin share the same pin hole, and the second pin occupies at least a portion of the inner space of the first pin, thereby facilitating saving the space of the shell.
    Type: Application
    Filed: January 16, 2025
    Publication date: March 19, 2026
    Inventors: Lei Wan, Chih-Kun Chen, Wen-Cong Zhang
  • Patent number: 12581439
    Abstract: A short-range communication method includes that a first node receives at least one piece of node information from at least one node; and the first node controls the first node to establish time-frequency synchronization with a second node that is in the at least one node and that belongs to a second synchronization area, where node information from the second node includes synchronization information of the second synchronization area, and the synchronization information indicates at least one of a node identifier, a synchronization status, or a synchronization direction between nodes in the second synchronization area.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: March 17, 2026
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xingqing Cheng, Lei Gao, Lei Wan, Changqing Yang, Jian Wang
  • Publication number: 20260047103
    Abstract: A magnetoresistive memory device includes a substrate, a bottom pinned spin-orbit torque (SOT) memory cell located over the substrate, and including a first magnetic tunnel junction and a common SOT layer located on the first magnetic tunnel junction, and a top pinned SOT memory cell located over the bottom pinned SOT memory cell, and including a second magnetic tunnel junction located on the common SOT layer. The common SOT layer is shared between the top pinned SOT memory cell and the bottom pinned SOT memory cell.
    Type: Application
    Filed: August 8, 2024
    Publication date: February 12, 2026
    Inventors: Lei WAN, Yabin FAN
  • Publication number: 20260047101
    Abstract: A spin-orbit-torque (SOT) magnetoresistive memory device includes a substrate, a first SOT magnetoresistive memory cell located in a first vertical level at a first vertical distance from the substrate, a second SOT magnetoresistive memory cell located in a second vertical level at a second vertical distance from the substrate which is different from the first vertical distance, and a bit line electrically connected to both the first and the second SOT magnetoresistive memory cells.
    Type: Application
    Filed: August 6, 2024
    Publication date: February 12, 2026
    Inventors: Lei WAN, Nathan FRANKLIN
  • Patent number: 12543508
    Abstract: A method of forming a memory device includes forming vertical stacks each including a respective first electrically conductive line and a respective selector rail over a substrate, such that the vertical stacks laterally extend along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction, forming magnetic tunnel junction material layers over the vertical stacks, and patterning the magnetic tunnel junction material layers and an upper portion of each of the selector rails to form a two-dimensional array of magnetic tunnel junctions and periodic notches at least in an upper portion of each of the selector rails.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 3, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Jordan Katine, Lei Wan
  • Patent number: 12526351
    Abstract: A Peripheral Component Interconnect Express (PCIe)-based data transmission method and apparatus includes a first node that encapsulates data into a transaction layer packet (TLP) and then sends the TLP to a second node, where the TLP includes a packet header part, a first field and a second field of the packet header part that are used to indicate first encapsulation information, and the first encapsulation information includes a data type of the data and at least one encapsulation parameter corresponding to the data type. The first field and the second field are used to indicate the information required for transmitting the data, so that the endpoints can communicate with each other even if the root is not used.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 13, 2026
    Assignee: SHENZHEN YINWANG INTELLIGENT TECHNOLOGIES CO., LTD.
    Inventors: Lei Wan, Pengxin Bao
  • Publication number: 20250393219
    Abstract: A device includes an array of magnetic unit cells located over a substrate, where each of the magnetic unit cells includes a magnetic tunnel junction, first nonmagnetic, electrically conductive lines electrically contacting respective row magnetic tunnel junctions, second nonmagnetic, electrically conductive lines contacting a respective column of magnetic tunnel junctions, and a soft magnetic material layer.
    Type: Application
    Filed: October 22, 2024
    Publication date: December 25, 2025
    Inventors: Lei WAN, Michael GROBIS, Jordan KATINE
  • Publication number: 20250384926
    Abstract: A magnetoresistive memory cell includes a magnetic polarizer layer having a hard magnetization along a hard magnetization direction, a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and including a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer. The memory cell also includes a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and including a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: December 18, 2025
    Inventors: Goran MIHAJLOVIC, Wonjoon JUNG, Lei WAN, Nathan FRANKLIN
  • Publication number: 20250384909
    Abstract: A magnetoresistive memory cell includes a magnetic polarizer layer having a hard magnetization along a hard magnetization direction, a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and including a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer. The memory cell also includes a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and including a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: December 18, 2025
    Inventors: Lei WAN, Goran MIHAJLOVIC, Wonjoon JUNG, Noraica DAVILA MELENDEZ
  • Publication number: 20250386523
    Abstract: A tunneling barrier resistor includes a first electrode layer containing a first nonmagnetic iron-group-containing alloy layer which includes a first refractory metal, a second electrode layer containing a second nonmagnetic iron-group-containing alloy layer which includes a second refractory metal, and a first tunneling barrier dielectric layer located between the first electrode layer and the second electrode layer.
    Type: Application
    Filed: July 16, 2024
    Publication date: December 18, 2025
    Inventors: Wonjoon JUNG, Michael GROBIS, Lei WAN, Hans RICHTER, James REINER, Tiffany SANTOS
  • Patent number: 12493205
    Abstract: An acousto-optic modulator enhanced by a sub-wavelength acoustic waveguide is provided. The acousto-optic modulator comprising: a substrate, wherein the substrate includes a sapphire underlayment and a silicon dioxide layer disposed on the sapphire underlayment; the substrate further including a lithium niobate thin film, wherein the lithium niobate thin film includes a transducer region and a tapered transition region that are etched, the sub-wavelength acoustic waveguide, an acoustic-photonic crystal cavity, and a side-coupled photonic crystal; wherein the etched transducer region is provided with an interdigital transducer, the sub-wavelength acoustic waveguide is connected with the etched transducer region via the tapered transition region that is etched, the acoustic-photonic crystal cavity is connected with a non-suspended sub-wavelength acoustic waveguide and is arranged parallel to a suspended side-coupled photonic crystal.
    Type: Grant
    Filed: May 15, 2025
    Date of Patent: December 9, 2025
    Assignee: NINGXIA UNIVERSITY
    Inventors: Lei Wan, Huilong Liu, Yuping Chen, Huipeng Chen
  • Patent number: 12482122
    Abstract: Disclosed is a method for constructing a bionic binocular active visual simultaneous localization and mapping (SLAM) system. The method includes: S1, constructing a binocular active visual system, peripheral vision is simulated using a panoramic camera, a panoramic value map is constructed based on the panoramic camera, and a binocular bionic eye gaze control strategy based on the panoramic value map is proposed; S2, designing a SLAM algorithm framework which is suitable for motion of the two bionic eyes, where relative pose optimization of left and right cameras based on a Perspective-n-Point algorithm and depth calculation for binocular matching points based on triangulation are adopted in a SLAM tracking thread; and S3, with the assistance of camera poses estimated by the SLAM system and sparse landmark point coordinates, training a self-supervised depth estimation network, to provide dense depth estimation for a mapping module of the SLAM system, achieving dense mapping.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: November 25, 2025
    Assignees: Jining University, Shanghai University
    Inventors: Jun Liu, Hengyu Li, Lei Wan, Jingyi Liu, Yueying Wang, Shaorong Xie, Jun Luo
  • Publication number: 20250331197
    Abstract: A method of forming a magnetoresistive memory array includes forming a stack structure including a one-dimensional array of first conductive lines laterally extending along a first horizontal direction, an array of magnetic tunnel junction stacks each containing a reference layer, a tunnel barrier layer, and a free layer located over the first conductive lines, and a two-dimensional array of sacrificial pillar structures located over the array of magnetic tunnel junction stacks, forming a dielectric matrix layer laterally surrounding the two-dimensional array of sacrificial pillar structures, forming a two-dimensional array of via cavities by removing the two-dimensional array of sacrificial pillar structures selective to the dielectric matrix layer, forming selector elements at least within volumes of the two-dimensional array of via cavities, and forming a one-dimensional array of second conductive lines laterally extending along a second horizontal direction over the selector elements.
    Type: Application
    Filed: April 23, 2024
    Publication date: October 23, 2025
    Inventors: Lei WAN, Neil ROBERTSON, Jordan KATINE
  • Patent number: 12423261
    Abstract: A PCIe-based communications method includes: a root complex writes identity information of a second node into a first node and writes routing table information into a third node, where the first node is a source node of first data, the second node is a destination node of the first data, and the third node is a node through which the first data arrives at the second node.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: September 23, 2025
    Assignee: Shenzhen Yinwang Intelligent Technologies Co., Ltd.
    Inventors: Lei Wan, Jiezuo Zhu, Xuehuan Wang, Pengxin Bao
  • Patent number: 12414307
    Abstract: Selector material layers are formed over the first electrically conductive lines, and magnetic tunnel junction material layers are formed over the selector material layers. The magnetic tunnel junction material layers are patterned into a two-dimensional array of magnetic tunnel junction (MTJ) pillar structures. A dielectric spacer material layer is deposited over the two-dimensional array of MTJ pillar structures. The dielectric spacer material layer and the selector material layers are anisotropically etched. Patterned portions of the selector material layers include a two-dimensional array of selector-containing pillar structures. Second electrically conductive lines are formed over the two-dimensional array of MTJ pillar structures.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: September 9, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Jordan Katine, Lei Wan
  • Patent number: 12402324
    Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: August 26, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Jordan Katine, Lei Wan
  • Patent number: 12328510
    Abstract: Disclosed is an active positioning method for bionic binocular vision during execution of a simultaneous localization and mapping (SLAM) task. The method includes: capturing a panoramic image using a panoramic camera and detecting key scene information; assigning values to pixels in the panoramic image to obtain a panoramic value map; projecting field-of-view areas of left and right bionic eye cameras separately onto the panoramic value map, to obtain a current binocular field-of-view projection area; calculating a mean value of the current binocular field-of-view projection area in the panoramic value map; comparing the mean value of the current binocular field-of-view projection area with a value threshold, and obtaining a binocular field-of-view projection area with a mean value higher than the value threshold by moving the binocular bionic cameras; and finally using a high-value image captured by the left and right bionic eye cameras as an input of a SLAM system.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: June 10, 2025
    Assignees: Jining University, Shanghai University
    Inventors: Jun Liu, Hengyu Li, Lei Wan, Jingyi Liu, Yueying Wang, Shaorong Xie, Jun Luo