Abstract: A carbon reduction assembly adapted for use with wet and dry coal combustion products (“CCPs”). The assembly includes a direct-fired carbon reduction section having a dry material inlet device that is adapted to receive the dry CCPs and a direct-fired carbon reduction section burner unit that is adapted to reduce carbon content in the dry CCPs. The assembly also includes a direct-fired dryer section that is operatively connected with the direct-fired carbon reduction section and has a wet material inlet device that is adapted to receive the wet CCPs and a direct-fired dryer section drum that is adapted to dry the wet CCPs. The assembly further includes a control unit that is operatively connected with the carbon reduction section and the dryer section. An amount of hot gas generated by the carbon reduction section is conveyed to the dryer section, and the assembly is adapted to produce dry fly ash.

Abstract: A carbon reduction assembly adapted for use with wet and dry coal combustion products (“CCPs”). The assembly includes a direct-fired carbon reduction section having a dry material inlet device that is adapted to receive the dry CCPs and a direct-fired carbon reduction section burner unit that is adapted to reduce carbon content in the dry CCPs. The assembly also includes a direct-fired dryer section that is operatively connected with the direct-fired carbon reduction section and has a wet material inlet device that is adapted to receive the wet CCPs and a direct-fired dryer section drum that is adapted to dry the wet CCPs. The assembly further includes a control unit that is operatively connected with the carbon reduction section and the dryer section. An amount of hot gas generated by the carbon reduction section is conveyed to the dryer section, and the assembly is adapted to produce dry fly ash.

Abstract: A method for producing an asphalt concrete blend that includes the steps of drying and heating aggregate in a single and only dryer, preferably via direct heating, and without use of a pre-dryer. The aggregate is then combined with asphalt cement, preferably via indirect heating, such that the blend has an asphalt cement components (ACC) percentage of at least 25% percent to form an aggregate mix. Liquid asphalt cement may also be added to the aggregate mix. Preferably, the asphalt cement content of the final asphalt concrete blend is provided by a maximum of 70% ACC. In certain cases, the asphalt cement content of the asphalt concrete blend is comprised of ACC and liquid asphalt cement.

Abstract: A method for producing an asphalt concrete blend that includes the steps of drying and heating aggregate in a single and only dryer, preferably via direct heating, and without use of a pre-dryer. The aggregate is then combined with asphalt cement, preferably via indirect heating, such that the blend has an asphalt cement components (ACC) percentage of at least 25% percent to form an aggregate mix. Liquid asphalt cement may also be added to the aggregate mix. Preferably, the asphalt cement content of the final asphalt concrete blend is provided by a maximum of 70% ACC. In certain cases, the asphalt cement content of the asphalt concrete blend is comprised of ACC and liquid asphalt cement.

Abstract: A dryer adapted for use in an asphalt plant. The dryer includes a drum having an inner wall and a flight having a proximal end connecting the flight to the inner wall of the drum and a distal end that is spaced apart from the proximal end. A first profile extends from the proximal end to the distal end of the flight and defines a flight shape. A notch is formed in the distal end of the flight, which notch includes a notch shape that is defined by a second profile. The second profile has a length L, a center point, and a portion that substantially approximates a conic section.

Abstract: A dryer adapted for use in an asphalt plant. The dryer includes a drum having an inner wall and a flight having a proximal end connecting the flight to the inner wall of the drum and a distal end that is spaced apart from the proximal end. A first profile extends from the proximal end to the distal end of the flight and defines a flight shape. A notch is formed in the distal end of the flight, which notch includes a notch shape that is defined by a second profile. The second profile has a length L, a center point, and a portion that substantially approximates a conic section.

Abstract: A buck switching regulator includes a feedback control circuit including a first gain circuit generating a first feedback signal indicative of the regulated output voltage; a ripple generation circuit generating a ripple signal that is injected to the first feedback signal; and a comparator receiving a first reference signal and the first feedback signal to generate a comparator output signal. The switching regulator further includes an offset compensation circuit including a second gain circuit generating a second feedback signal indicative of the regulated output voltage; and an operational transconductance amplifier (OTA) configured to receive the second feedback signal and the first reference signal and to generate an output signal. The output signal of the OTA is coupled to the comparator to adjust an offset to the comparator so as to cancel the offset at the regulated output voltage due to the injected ripple signal.

Abstract: A buck switching regulator includes a feedback control circuit including a balanced feedback network including first and second gain circuits configured to generate first and second feedback signals, respectively, indicative of the regulated output voltage; a ripple generation circuit configured to inject a first ripple signal to the first gain circuit and a second ripple signal to the second gain circuit; an operational transconductance amplifier (OTA) configured to receive the second feedback signal and a reference signal and to generate an output signal being coupled to a node in the feedback control circuit; and a comparator configured to receive the first feedback signal and a comparator reference signal and to generate a comparator output signal. The output signal of the OTA is applied to the feedback control circuit to cancel a voltage offset in the regulated output voltage due to the injected ripple signal to the first gain circuit.

Abstract: A buck switching regulator includes a feedback control circuit including a feedback network including first and second gain circuits configured to generate first and second feedback signals, respectively, indicative of the regulated output voltage; a ripple generation circuit configured to inject a ripple signal to the first gain circuit; an operational transconductance amplifier (OTA) configured to receive the second feedback signal and a reference signal and to generate an output signal being coupled to the first gain circuit to adjust the first feedback signal; and a comparator configured to receive the first feedback signal and the reference signal and to generate a comparator output signal. The output signal of the OTA is applied to the first feedback signal to cancel a voltage offset in the regulated output voltage due to the injected ripple signal to the first gain circuit.

Abstract: A buck switching regulator includes a feedback control circuit including a balanced feedback network including first and second gain circuits configured to generate first and second feedback signals, respectively, indicative of the regulated output voltage; a ripple generation circuit configured to inject a first ripple signal to the first gain circuit and a second ripple signal to the second gain circuit; an operational transconductance amplifier (OTA) configured to receive the second feedback signal and a reference signal and to generate an output signal being coupled to a node in the feedback control circuit; and a comparator configured to receive the first feedback signal and a comparator reference signal and to generate a comparator output signal. The output signal of the OTA is applied to the feedback control circuit to cancel a voltage offset in the regulated output voltage due to the injected ripple signal to the first gain circuit.

Abstract: A buck switching regulator includes a feedback control circuit including a feedback network including first and second gain circuits configured to generate first and second feedback signals, respectively, indicative of the regulated output voltage; a ripple generation circuit configured to inject a ripple signal to the first gain circuit; an operational transconductance amplifier (OTA) configured to receive the second feedback signal and a reference signal and to generate an output signal being coupled to the first gain circuit to adjust the first feedback signal; and a comparator configured to receive the first feedback signal and the reference signal and to generate a comparator output signal. The output signal of the OTA is applied to the first feedback signal to cancel a voltage offset in the regulated output voltage due to the injected ripple signal to the first gain circuit.

Abstract: A buck switching regulator includes a feedback control circuit including a first gain circuit generating a first feedback signal indicative of the regulated output voltage; a ripple generation circuit generating a ripple signal that is injected to the first feedback signal; and a comparator receiving a first reference signal and the first feedback signal to generate a comparator output signal. The switching regulator further includes an offset compensation circuit including a second gain circuit generating a second feedback signal indicative of the regulated output voltage; and an operational transconductance amplifier (OTA) configured to receive the second feedback signal and the first reference signal and to generate an output signal. The output signal of the OTA is coupled to the comparator to adjust an offset to the comparator so as to cancel the offset at the regulated output voltage due to the injected ripple signal.

Abstract: The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film.

Abstract: The present invention relates to a method for trimming passive devices during fabrication to account for process variations. More particularly, the present invention relates to a method by which an adjustable device layer comprised within a passive device (e.g., resistor body, capacitor electrodes) can be measured and subsequently trimmed (e.g., etched to reduce size) during processing to correct for process variations. Essentially, an operational parameter is measured for a plurality of passive devices. The measurements are used to form an adjustment map for a region of a semiconductor body (e.g., wafer) comprising information pertaining to operational parameters as a function of spatial coordinates. The adjustment map is utilized by a DMD projector configured to pattern openings into a hardmask configured over the adjustable device layer. The adjustable device layer is then etched in regions not protected by the hardmask, thereby effectively trimming the passive device according to the adjustment map.

Abstract: The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film.

Abstract: The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.

Abstract: The invention provides thermally enhanced BGAs and methods for their fabrication with a ground ring suitable for operably coupling to either the frontside or backside, or both, of an IC chip mounted on a substrate. The methods and devices of the invention disclosed include the fabrication of a ground ring on the surface of a BGA substrate prepared for receiving the frontside of the chip. A heat spreader has ground ring corresponding to substrate round ring and is attached at the backside of the chip with a conductive material. A conductive material is interposed between the heat spreader and substrate ground rings, electrically coupling them. Thus, the backside of the chip may be electrically connected to the ground ring as well as, or instead of, the frontside.

Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.

Abstract: The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate stricture (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.

Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.