Abstract: A Schottky device comprises a substrate layer of a first conductivity type having a surface, a guard ring formed over the surface of the substrate layer and surrounding a barrier region of the substrate layer. The guard ring comprises a gate of a second conductivity type disposed over a dielectric layer. A metal can be formed over the barrier region to form a Schottky junction.

Abstract: According to one embodiment of the invention, a method of packaging ball grid arrays includes providing a substrate having a plurality of holes formed therein. Each hole is associated with a respective one of a plurality of contact pads formed on a first surface of the substrate. The method further includes disposing a plurality of balls within respective ones of the plurality of holes such that at least a portion of each ball projects outwardly from the first surface, and applying a force to each of the balls from above the first surface to couple the balls to the substrate.

Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).

Abstract: According to one embodiment of the invention, a method of stud bumping includes providing a bonding head having a plurality of wire passages formed therein, disposing a plurality of wires through respective ones of the plurality of wire passages, providing a substrate having a plurality of bond pads, engaging the wires with respective ones of a first set of the bond pads, and forming a first set of stud bumps outwardly from respective ones of the first set of the bond pads.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A system and methodology for fabricating integrated circuits (ICs) on wafer die monitors at a subset of die one or more parameters that can affect the performance capabilities of associated ICs. One or more respective parameters for unmeasured die are derived based on one or more of the measured parameter. Fuses are selectively set for ICs at each die location based on parameters associated with each respective die location, thereby configuring the respective ICs accordingly.

Abstract: In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common mode noise can decrease the frequency at which these signals are clocked. The use of slots 620 formed in the ground (or power plane) 609 of the substrate and lying perpendicularly (and equally spaced) underneath the differential pair 605 improves the common mode rejection of the differential pair 605 by increasing the common mode impedance without affecting the differential mode impedance. The use of slots 620 does not require modifications to the packaging, and only minor modifications to the substrate.

Abstract: An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector structure. The emitter 36 is adjacent to and overlies the base 32 and the base 32 is adjacent to and overlies a core portion 48 of the collector structure. The collector structure includes, in addition to the core portion 48, a collector contact region 31 and a lateral collector region 50 between the core portion 48 and the collector contact region 31. The lateral collector region 50 is thinner than said collector contact region at some point along its length.

Abstract: A system and methodology for fabricating integrated circuits (ICs) on wafer die monitors at a subset of die one or more parameters that can affect the performance capabilities of associated ICs. One or more respective parameters for unmeasured die are derived based on one or more of the measured parameter. Fuses are selectively set for ICs at each die location based on parameters associated with each respective die location, thereby configuring the respective ICs accordingly.

Abstract: In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common mode noise can decrease the frequency at which these signals are clocked. The use of slots 620 formed in the ground (or power plane) 609 of the substrate and lying perpendicularly (and equally spaced) underneath the differential pair 605 improves the common mode rejection of the differential pair 605 by increasing the common mode impedance without affecting the differential mode impedance. The use of slots 620 does not require modifications to the packaging, and only minor modifications to the substrate.

Abstract: An integrated circuit and a method of fabricating the same are disclosed. Complementary bipolar transistors (20p, 20n) are fabricated as vertical bipolar transistors. The emitter polysilicon (35), which is in contact with the underlying single-crystal base material, is doped with a dopant for the appropriate device conductivity type, and also with a diffusion retardant, such as elemental carbon, SiGeC, nitrogen, and the like. The diffusion retardant prevents the dopant from diffusing too fast from the emitter polysilicon (35). Device matching and balance is facilitated, especially for complementary technologies.

Abstract: An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector structure. The emitter 36 is adjacent to and overlies the base 32 and the base 32 is adjacent to and overlies a core portion 48 of the collector structure. The collector structure includes, in addition to the core portion 48, a collector contact region 31 and a lateral collector region 50 between the core portion 48 and the collector contact region 31. The lateral collector region 50 is thinner than said collector contact region at some point along its length.

Abstract: A CMP machine (100, 200, 300) and/or process that uses selective heating of the polishing pad/belt (120, 220, 320) to improve uniformity. A heating mechanism (110) is used to heat a selected area such as the perimeter (130, 230, 330) of the pad or belt (120, 220, 320). Heating the selected area improves the removal rate in that area. For example, heating along the perimeter of the pad (120, 220, 320) improves the removal rate at the perimeter of the semiconductor wafer (150).

Abstract: A CMP machine (100, 200, 300) and/or process that uses selective heating of the slurry (160) to improve uniformity. A temperature control mechanism (110) is used to heat and/or cool slurry (160) applied to a selected area of the pad or belt (120, 220, 320). Heating in the selected area improves the removal rate in that area, whereas cooling decreases the removal rate in that area. For example, heating along the perimeter of the pad (120, 220) improves the removal rate at the perimeter of the semiconductor wafer (150).

Abstract: Contaminants are removed from particulate material in an inclined, rotating drum which has an inlet for contaminated material at its upper end, an outlet at its upper end for vaporized contaminants, an inlet for air that is located between the upper end and the lower end, and an outlet for clean particulate material at its lower end. Contaminated particulate material is admitted to the upper end of the drum and conveyed under the influence of gravity and the rotation of the drum to its lower end. A combustion chamber at the lower end of the drum is provided with an air inlet, a fuel burner and an outlet for combustion products. Fuel is burned in the combustion chamber with excess air supplied so that the temperature of the products of combustion is high enough to volatilize the contaminants in the particulate material, but not so high as to incinerate them. A fire tube within the drum conveys the combustion products from the combustion chamber to the upper end of the drum.