Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.

Abstract: A transistor apparatus includes a silicon substrate and a barrier structure extending substantially from generally adjacent the silicon substrate to a locus displaced from the silicon substrate. The barrier structure generally surrounds a volume containing connection loci for the transistor apparatus and a buried layer in a silicon medium. The connection loci and the buried layer occupy a space generally presenting a first lateral expanse generally parallel with the silicon substrate. The volume presents a second lateral expanse generally parallel with the silicon substrate. The second lateral expanse is greater than the first lateral expanse within a predetermined distance of the substrate.

Abstract: The invention provides thermally enhanced BGAs and methods for their fabrication with a ground ring suitable for operably coupling to either the frontside or backside, or both, of an IC chip mounted on a substrate. The methods and devices of the invention disclosed include the fabrication of a ground ring on the surface of a BGA substrate prepared for receiving the frontside of the chip. A heat spreader has ground ring corresponding to substrate round ring and is attached at the backside of the chip with a conductive material. A conductive material is interposed between the heat spreader and substrate ground rings, electrically coupling them. Thus, the backside of the chip may be electrically connected to the ground ring as well as, or instead of, the frontside.

Abstract: A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is employed to implant a dopant into the target deep well region to form a deep well region with the selected region having a lowered dopant concentration. The lowered dopant concentration can yield a higher breakdown voltage for the bipolar device. The intrinsic dilute mask mitigates implantation within the selected region.

Abstract: The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A poly resistor mask having a selected percentage of the poly resistor exposed is formed on the poly resistor (110). A selected dopant is implanted (112), which modifies the resistivity of the poly resistor. The mask is removed (114) and a thermal activation process is performed (116) that diffuses the implanted dopant to a substantially uniform concentration throughout the polysilicon resistor.

Abstract: System and method for limiting an output signal of a differential amplifier. A preferred embodiment comprises a limit sense amplifier configured to detect when the output exceeds a permitted limit, a common mode bias current unit configured to increase a signal gain of a common mode amplifier in the differential operational amplifier when the limit sense amplifier detects that the output exceeded the permitted limit, and an output stage bias current unit configured to fix the output at a level substantially equal to the specified limit when the limit sense amplifier detects that the output exceeded the permitted limit. The clamping is achieved by changing the operation of circuitry within the differential amplifier and results in a smoother clamping that helps to maintain stable operation.

Abstract: An apparatus for effecting signal chopping in an amplifier device having an amplifier section, a modulation section, a ramp generating section and a clock section includes: at least one signal treating unit coupled among the clock section, the amplifier section and the ramp generating section. The at least one signal treating unit cooperates with the clock section to effect providing a chopping signal to the amplifying unit at a chopping frequency and to effect providing a ramping signal at a ramping frequency to the ramp generating section. The chopping frequency is neither a fundamental frequency nor a harmonic frequency of the ramping frequency.

Abstract: The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A poly resistor mask having a selected percentage of the poly resistor exposed is formed on the poly resistor (110). A selected dopant is implanted (112), which modifies the resistivity of the poly resistor. The mask is removed (114) and a thermal activation process is performed (116) that diffuses the implanted dopant to a substantially uniform concentration throughout the polysilicon resistor.

Abstract: A semiconductor device comprising a metallic leadframe (103) with a first surface (103a) and a second surface (103b). The leadframe includes a chip pad (104) and a plurality of segments (107); the chip pad is held by a plurality of straps (105), wherein each strap has a groove (106). A chip (101) is mounted on the chip pad and electrically connected to the segments. A heat spreader (110) is disposed on the first surface of the leadframe; the heat spreader has its central portion (110a) spaced above the chip connections (108), and also has positioning members (110b) extending outwardly from the edges of the central portion so that they rest in the grooves of the straps. Encapsulation material surrounds the chip, the electrical connections, and the spreader positioning members, and fills the space between the spreader and the chip, while leaving the second leadframe surface and the central spreader portion exposed.

Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. The method comprises forming a silicon-on-insulator (SOI) wafer. The SOI wafer has a carrier silicon layer, an oxide layer disposed outwardly from the carrier silicon layer, and a silicon layer disposed outwardly from the oxide layer. The method also includes forming at least one feature at least partially in the silicon layer. The method also includes separating the carrier silicon layer from the silicon layer by chemically removing the oxide layer.

Abstract: A semiconductor device comprising a metallic leadframe (103) with a first surface (103a) and a second surface (103b). The leadframe includes a chip pad (104) and a plurality of segments (107); the chip pad is held by a plurality of straps (105), wherein each strap has a groove (106). A chip (101) is mounted on the chip pad and electrically connected to the segments. A heat spreader (110) is disposed on the first surface of the leadframe; the heat spreader has its central portion (110a) spaced above the chip connections (108), and also has positioning members (110b) extending outwardly from the edges of the central portion so that they rest in the grooves of the straps. Encapsulation material surrounds the chip, the electrical connections, and the spreader positioning members, and fills the space between the spreader and the chip, while leaving the second leadframe surface and the central spreader portion exposed.

Abstract: We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A method comprising coupling a substrate interconnect to a substrate pad, attaching at least two flip chips to said substrate interconnect to electrically connect together said chips, and coupling at least one lead to each of the chips.

Abstract: A Schottky device having a substrate layer of a first conductivity type having a surface, and a guard ring formed over the surface of the substrate layer and also surrounding a barrier region of the substrate layer. The guard ring has a gate of a second conductivity type disposed over a dielectric layer. A metal can be formed over the barrier region to form a Schottky junction.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A silicided amorphous polysilicon-metal capacitor is formed using a standard process except that the exposed surface of the polycrystalline silicon is transformed into amorphous polysilicon before the silicidation of the polysilicon layer to form the bottom plate of the capacitive element. Transforming the polycrystalline silicon to amorphous polysilicon at the surface renders the top surface of the polysilicon substantially smooth compared to that of the polycrystalline silicon. This in turn renders the surface of the silicide layer, which forms the bottom plate of the capacitor and is formed by the silicidation of the polysilicon, to be substantially smooth as well. Thus, the likelihood of stress points being formed in the dielectric layer of the capacitor is substantially reduced, increasing yield and reliability and permitting a reduction in the thickness which leads to a greater value of capacitance per unit area.

Abstract: A method for assembling a whole semiconductor wafer (101) with a plurality of device units (120) having metal contact pads. Each contact pad has a patterned barrier metal layer and a metal stud (103, preferably copper or nickel) with an outer surface suitable to form metallurgical bonds without melting. A leadframe suitable for the whole wafer is provided, which has a plurality of segments groups (102), each group suitable for one device unit; each segment has first (102a) and second ends (102b) covered by solderable metal. A predetermined amount of solder paste (104) is placed on each of the first segment ends. The leadframe is then aligned with the wafer so that each of the paste-covered segment ends is aligned with the corresponding metal stud of the respective device unit. The leadframe is connected to the wafer and the whole wafer is encapsulated (105) so that the device units and the first segment ends are covered, while the second segment ends remain exposed.

Abstract: In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of the chips (101). Thereafter, the fabrication of the active first wafer surface is completed and protected. Then, the wafer is flipped to expose the second wafer surface (103), and the wafer is subjected to a cutting saw. The saw is aligned with the trenches in the first surface so that the saw cuts the second surface along streets (106), which extend the trenches through the wafer. The saw is stopped cutting at a depth (105b), when the saw streets just coalesce with the trench streets, respectively, whereby the chips are completely singulated.

Abstract: A semiconductor circuit comprising a semiconductor die and a package substrate. In one embodiment, a first plurality of conductive bumps serves as a portion of a conductive path between contacts on the semiconductor die and contacts on the package substrate. A second plurality of conductive bumps serves as a portion of a conductive path between other contacts on the die and contacts on the package substrate. Each of the bumps in the first plurality of conductive bumps is larger than each of the bumps in the second plurality of conductive bumps. In another embodiment, the average size of the first plurality of conductive bumps may be at least 20% larger (or greater) than the average size of the second plurality of bumps.