Abstract: In one embodiment, a medical device includes a tissue suction housing and a moveable member disposed in the tissue suction housing. The tissue suction housing has a proximal end and a distal end. The distal end has an opening and the tissue suction housing has at least two suturing device openings. The tissue suction housing is configured to pull up bodily tissue through the opening in the distal end when placed under a vacuum and to receive a suturing device through one of the suturing device openings.

Abstract: The present invention includes an improved sprinkler design having a magnetic sensing system for determining the position of the riser nozzle, a waterproofed motor housing and related cables, configurable sprinkler body compartments, and a pilot valve with a check valve assembly, both of which are located within the sprinkler body.

Abstract: A stiff anti-backlash gear unit comprising two or more high ratio reducer assemblies provides an energy efficient, low backlash, speed reducer. The gear unit is assembled in such a way as to eliminate backlash without any preloading and may be configured as a conventional, planetary or star gear with co-axial, spaced, angled or multiple output shafts.

Abstract: A planetary gear pump comprising a central gear and a plurality of planet pairs provides a space efficient transducer between hydraulic and mechanical energy. When it is configured as a pump, a high flow rate is provided. When it is configured as an actuator, a high torque is provided. A dual-stage configuration may be used as a low speed high torque actuator with high energy efficiency, high pitch velocity, and low slippage.

Abstract: The present invention includes an improved sprinkler design having a magnetic sensing system for determining the position of the riser nozzle, a waterproofed motor housing and related cables, configurable sprinkler body compartments, and a pilot valve with a check valve assembly, both of which are located within the sprinkler body.

Abstract: The present invention includes an improved sprinkler design having a magnetic sensing system for determining the position of the riser nozzle, a waterproofed motor housing and related cables, configurable sprinkler body compartments, and a pilot valve with a check valve assembly, both of which are located within the sprinkler body.

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

Abstract: A cup holder that suspends a beverage below a human wrist. A wrist strap is connected by a preferably flexible suspension to a beverage support. The device may be adjusted for different sized wrists and cups and to modify the distance between the cup and the wrist. The user may release the cup at any time and it will be supported below the wrist by the invention. Angling the wrist downward automatically delivers the cup into the hand of the user. While the cup is supported, the user may rotate and swing their arm freely without upsetting the orientation of the cup. Use of this cup holder requires no visual ability.

Abstract: An example approach is provided for managing service requests. An input, from a device of a user, for a service request associated with a specified service and/or a product is processed.

Abstract: An example approach is provided for generating and managing service requests. One or more service requests are generated. Further, the one or more requests are assigned to one or more service providers and are aggregated. Furthermore, one or more updates are presented on at least a portion of the aggregation.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

Abstract: A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: The present invention includes an improved sprinkler design having a magnetic sensing system for determining the position of the riser nozzle, a waterproofed motor housing and related cables, configurable sprinkler body compartments, and a pilot valve with a check valve assembly, both of which are located within the sprinkler body.

Abstract: The present invention includes an improved sprinkler design having a magnetic sensing system for determining the position of the riser nozzle, a waterproofed motor housing and related cables, configurable sprinkler body compartments, and a pilot valve with a check valve assembly, both of which are located within the sprinkler body.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry.

Abstract: A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.