Patents by Inventor Leo James

Leo James has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6970976
    Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (Li) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information).
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: November 29, 2005
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie
  • Patent number: 6823471
    Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steve Dodson, Guy Lynn Guthrie, Jerry Don Lewis
  • Publication number: 20040162570
    Abstract: A surgical assist device used to constrict blood perfusion during surgeries is provided. The device utilizes one or more compression members to apply a controlled pressure to an open artery to stop blood perfusion at the surgical site. The compression members can be deployed and retracted manually, automatically, or remotely. The applied pressure can also be remotely monitored and controlled. The device can be used in conjunction with existing suction based coronary stabilization devices or used as a stand-along unit. The device can be used to apply controlled pressure to the arteries to constrict blood perfusion with significantly less invasion into the surgical area.
    Type: Application
    Filed: January 22, 2003
    Publication date: August 19, 2004
    Inventors: Hitendu H. Dave, Jeffrey B. Jump, Leo James Lichte, Marko Turina, Gregor Zund
  • Patent number: 6658556
    Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steve Dodson, Guy Lynn Guthrie, Jerry Don Lewis
  • Patent number: 6606666
    Abstract: An information handling system includes a producer that outputs packets, a buffer that receives packets from the producer, buffers the packets, and eventually outputs the packets, and a control unit that controls the flow of packets from the producer to the buffer. The control unit receives as inputs a producer output indication indicating that the producer has output a packet to the buffer and a buffer output indication indicating that the buffer has output a packet. Based upon a capacity of the buffer, a number of the producer output indications, a number of buffer output indications, and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. In response to a determination that the producer can output a packet without packet loss, the control unit outputs a grant message to the producer indicating that the producer is permitted to output a packet.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: August 12, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Henry Bell, Jr., Robert Alan Cargnoni, Leo James Clark, William John Starke
  • Patent number: 6604145
    Abstract: An information handling system includes a plurality of producers that output packets of information, at least one consumer of the packets, and an information pipeline coupling the consumer and at least a particular producer among the plurality of producers. The information pipeline includes a shared resource having a bandwidth shared by multiple of the plurality of producers. The information handling system further includes a control unit that regulates packet output of the particular producer and that receives as inputs a producer output indication indicating that the particular producer output a packet and a shared resource input indication indicating that a packet output by the particular producer has been accepted by the shared resource for transmission to the consumer.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: August 5, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Henry Bell, Jr., Robert Alan Cargnoni, Leo James Clark, William John Starke
  • Patent number: 6601105
    Abstract: An information handling system includes a producer that outputs packets of information, a plurality of buffers that can each receive packets from the producer and output the packets, and a control unit. The control unit receives at least one producer output indication indicating whether the producer output a packet to one of the plurality of buffers and a plurality of buffer output indications that each indicate whether a respective one of the plurality of buffers has output a packet. Based upon capacities of the plurality of buffers, the producer output indications, the buffer output indications and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. If so, the control unit provides a grant message to the producer indicating that the producer is permitted to output a packet.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Henry Bell, Jr., Robert Alan Cargnoni, Leo James Clark, William John Starke
  • Patent number: 6598086
    Abstract: An information handling system includes a plurality of sequentially connected units including a first unit, a second unit and a third unit. Packets of information flow from the first unit directly to the second unit and then to the third unit, and each of the plurality of units provides a respective dynamic output indication indicating if that unit output a packet. The information handling system further includes a control unit that determines, utilizing all of the plurality of dynamic output indications, packet buffering capacities of the plurality of units, and guaranteed packet flows between adjacent ones of the plurality of units, if the first unit can output a packet directly to the second unit without packet loss. In response to this determination, the control unit outputs a control signal to the first unit.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: July 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Henry Bell, Jr., Robert Alan Cargnoni, Leo James Clark, William John Starke
  • Patent number: 6598118
    Abstract: A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space. In one preferred embodiment, the execution units of the processor include a number of load-store units (LSUs) that each process only instructions that access data having associated addresses within a respective one of the plurality of address subsets. The processor may further be incorporated within a data processing system having a number of interconnects and a number of sets of system memory hardware that each have affinity to a respective one of the plurality of address subsets.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: July 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steve Dodson, Guy Lynn Guthrie, Jerry Don Lewis
  • Patent number: 6581115
    Abstract: A data processing system with configurable processor chip buses. The processor chip is designed with a plurality of extended buses of which a number are configurable buses (i.e., capable of being allocated to one of several external components, particularly memory and other SMPs). The processor chip allows for the static allocation of these configurable buses to these external components, based primarily on vendor system design preferences.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: June 17, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, James Steven Fields, Jr.
  • Patent number: 6553447
    Abstract: A Fully Interconnected System Architecture (FISA) for an improved data processing system. The data processing system topology has a processor chip and external components to the processor chip, such as memory and input/output (I/O) and other processor chips. The processor chip is interconnected to the external components via a point-to-point bus topology controlled by an intra-chip integrated, distributed switch (IDS) controller. The IDS controller provides the chip with the functionality to provide a single bus to each external component and provides an overall total bandwidth greater than traditional topologies while reducing latencies between the processor and the external components. The design of the processor chip with the intra-chip IDS controller provides a pseudo “distributed switch” which may separately access distributed external components, such as memory and I/Os, etc.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: April 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, Jerry Don Lewis, Bradley McCredie
  • Patent number: 6535939
    Abstract: A data processing system with configurable processor chip buses. The processor chip is designed with a bus allocation unit and has a plurality of extended buses of which a number are configurable buses (i.e. may be dynamically allocated to any one of several external components, particularly memory and other SMPs). A priority determination of bandwidth requirements of the external components is made during system processing. Then the configurable buses are dynamically allocated to the external components based on their bandwidth requirement and/or the configuration which provides the best overall system efficiency.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: March 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, James Steven Fields, Jr.
  • Patent number: 6532521
    Abstract: A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie, James Stephen Fields, Jr.
  • Patent number: 6516404
    Abstract: A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: February 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steve Dodson, Guy Lynn Guthrie, Jerry Don Lewis
  • Patent number: 6510494
    Abstract: A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the pref etch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: January 21, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie, James Stephen Fields, Jr.
  • Patent number: 6496921
    Abstract: A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie, James Stephen Fields, Jr.
  • Patent number: 6487637
    Abstract: A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. Further branch predictions or stream associations that were made based on an earlier speculative choice are linked by using a tag pool which assigns a bit fields in the tag pool entries to the level of speculation depth. Each entry shares in common the bit field values associated with earlier branches or stream associations.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: November 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie, William John Starke
  • Patent number: 6473833
    Abstract: A method of operating a multi-level memory hierarchy of a computer system and an apparatus embodying the method, wherein multiple levels of storage subsystems are used to improve the performance of the computer system, each next higher level generally having a faster access time, but a smaller amount of storage. Values within a level are indexed by a directory that provides an indexing of information relating the values in that level to the next lower level. In a preferred embodiment of the invention, the directories for the various levels of storage are contained within the next higher level, providing a faster access to the directory information. Cache memories used as the highest levels of storage, and one or more sets are allocated out of that cache memory for containing a directory of the next lower level of storage.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, James Stephen Fields, Jr., Lakshminarayana Baba Arimilli
  • Patent number: 6470442
    Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: October 22, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steve Dodson, Guy Lynn Guthrie, Jerry Don Lewis
  • Patent number: 6463507
    Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information).
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie