Patents by Inventor Leo M. Higgins
Leo M. Higgins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446476Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.Type: GrantFiled: March 19, 2018Date of Patent: October 15, 2019Assignee: NXP USA, Inc.Inventors: Leo M. Higgins, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, Jr., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
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Patent number: 10347534Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.Type: GrantFiled: September 12, 2017Date of Patent: July 9, 2019Assignee: NXP B.V.Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Michael Zernack, Leo M. Higgins, III
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Patent number: 10325876Abstract: The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure.Type: GrantFiled: June 25, 2014Date of Patent: June 18, 2019Assignee: NXP USA, Inc.Inventors: Varughese Mathew, Burton J. Carpenter, Leo M. Higgins, III, Chu-Chung Lee, Tu-Anh N. Tran
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Patent number: 10249557Abstract: A packaged lead frame includes a encapsulant having a first minor side, a second minor side opposite the first minor side, a third minor side, and a fourth minor side opposite the third minor side, and a plurality of leads along the third minor side between the first minor side and a center plane between the first and second minor side. The plurality of leads extend outwardly from the encapsulant at a first plane. Each of the plurality of leads includes a corresponding jog external to the encapsulant which jogs away from the center plane, wherein the corresponding jog of each lead from a first lead of the plurality of leads closest to the center plane to a last lead of the first plurality of leads closest to the first minor side jogs incrementally further away the center plane.Type: GrantFiled: May 23, 2017Date of Patent: April 2, 2019Assignee: NXP USA, Inc.Inventors: Leo M. Higgins, III, Burton Jesse Carpenter
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Patent number: 10242935Abstract: A packaged semiconductor device includes a die attached to a die flag of a lead frame wherein the die includes a first, second, third, and fourth minor side, wherein the first and second minor sides are opposite each other and the third and fourth minor sides are opposite each other. The device includes an outer-most lead of the lead frame extending outwardly from the first minor side of the die and closest to the third minor side, wherein the outer-most lead includes a thinned region located between the die and a full thickness portion of the outer-most lead. The device includes an electrical connection between the die and the outer-most lead, and an encapsulant surrounding the die, the electrical connection, and surrounding at least a portion of an outer edge of the thinned portion of the outer-most lead such that the full thickness portion of the outer-most lead extends beyond the encapsulant.Type: GrantFiled: August 31, 2017Date of Patent: March 26, 2019Assignee: NXP USA, Inc.Inventors: Burton Jesse Carpenter, Leo M. Higgins, III
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Publication number: 20190088576Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.Type: ApplicationFiled: March 19, 2018Publication date: March 21, 2019Inventors: LEO M. HIGGINS, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, JR., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
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Publication number: 20190080963Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.Type: ApplicationFiled: September 12, 2017Publication date: March 14, 2019Inventors: Martin LAPKE, Hartmut Buenning, Sascha MOELLER, Guido ALBERMANN, Michael ZERNACK, Leo M. HIGGINS, III
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Publication number: 20190067172Abstract: A packaged semiconductor device includes a die attached to a die flag of a lead frame wherein the die includes a first, second, third, and fourth minor side, wherein the first and second minor sides are opposite each other and the third and fourth minor sides are opposite each other. The device includes an outer-most lead of the lead frame extending outwardly from the first minor side of the die and closest to the third minor side, wherein the outer-most lead includes a thinned region located between the die and a full thickness portion of the outer-most lead. The device includes an electrical connection between the die and the outer-most lead, and an encapsulant surrounding the die, the electrical connection, and surrounding at least a portion of an outer edge of the thinned portion of the outer-most lead such that the full thickness portion of the outer-most lead extends beyond the encapsulant.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventors: Burton Jesse Carpenter, Leo M. Higgins, III
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Publication number: 20180342444Abstract: A packaged lead frame includes a encapsulant having a first minor side, a second minor side opposite the first minor side, a third minor side, and a fourth minor side opposite the third minor side, and a plurality of leads along the third minor side between the first minor side and a center plane between the first and second minor side. The plurality of leads extend outwardly from the encapsulant at a first plane. Each of the plurality of leads includes a corresponding jog external to the encapsulant which jogs away from the center plane, wherein the corresponding jog of each lead from a first lead of the plurality of leads closest to the center plane to a last lead of the first plurality of leads closest to the first minor side jogs incrementally further away the center plane.Type: ApplicationFiled: May 23, 2017Publication date: November 29, 2018Inventors: Leo M. HIGGINS, III, Burton Jesse CARPENTER
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Patent number: 10037965Abstract: A semiconductor device includes a plurality of wire bonds formed on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; a protective material is applied around the plurality of wire bonds, the protective material having a first pH; and at least a portion of the semiconductor device and the protective material are encapsulated with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.Type: GrantFiled: October 20, 2016Date of Patent: July 31, 2018Assignee: NXP USA, Inc.Inventor: Leo M. Higgins, III
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Patent number: 9935079Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.Type: GrantFiled: December 8, 2016Date of Patent: April 3, 2018Assignee: NXP USA, Inc.Inventors: Chee Seng Foong, Trent Uehling, Leo M. Higgins, III
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Patent number: 9899290Abstract: A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes encapsulated material on the major side and an inner area where there is a lack of encapsulant over a portion of the device at the major side. The extended structure prevents encapsulant from getting into the inner area during the encapsulating process.Type: GrantFiled: March 23, 2016Date of Patent: February 20, 2018Assignee: NXP USA, INC.Inventor: Leo M. Higgins, III
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Publication number: 20170278768Abstract: A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes encapsulated material on the major side and an inner area where there is a lack of encapsulant over a portion of the device at the major side. The extended structure prevents encapsulant from getting into the inner area during the encapsulating process.Type: ApplicationFiled: March 23, 2016Publication date: September 28, 2017Inventor: Leo M. Higgins, III
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Patent number: 9685351Abstract: A method and apparatus are described for fabricating a microchip structure (70) which protects interior electrical integrated circuits and components (120) attached to a lead frame die flag (104) using a molding compound (124) that mechanically interlocks with one or more positive mold lock structures formed as dummy wire loops (114) or stud bumps (214) that are attached to the lead frame (100) and/or die flag (104).Type: GrantFiled: July 18, 2014Date of Patent: June 20, 2017Assignee: NXP USA, INC.Inventor: Leo M. Higgins, III
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Publication number: 20170040282Abstract: A semiconductor device includes a plurality of wire bonds formed on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; a protective material is applied around the plurality of wire bonds, the protective material having a first pH; and at least a portion of the semiconductor device and the protective material are encapsulated with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventor: Leo M. HIGGINS, III
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Patent number: 9508622Abstract: A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.Type: GrantFiled: April 28, 2011Date of Patent: November 29, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Leo M. Higgins, III
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Patent number: 9470652Abstract: A sensing device includes a sensor die having a sensing region formed at a first surface of the sensor die. The sensing device further includes an encapsulant covering the sensing die, the encapsulant having a cavity formed therein, wherein the cavity exposes the sensing region. A sensitive membrane material is deposited within the cavity over the sensing region. A method of manufacturing sensing devices entails mounting a plurality of sensing dies to a carrier, encapsulating the dies in an encapsulant, forming cavities in the encapsulant, the cavities exposing a sensing region of each sensor die, and depositing the sensitive membrane material within each of the cavities. The encapsulating and forming operations can be performed simultaneously using a film-assisted molding (FAM) process, and the depositing operation is performed following FAM at an ambient temperature that is lower than the temperature needed to perform FAM.Type: GrantFiled: September 15, 2015Date of Patent: October 18, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Stephen R. Hooper, Leo M. Higgins, III, Raymond M. Roop
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Patent number: 9461009Abstract: A method of packaging a semiconductor device is described. The method includes: attaching a first surface of a semiconductor die to a carrier; forming one or more first stud bumps on the carrier; using bond wires, electrically connecting one or more locations on a second surface of the semiconductor die to one or more first stud bumps; molding the semiconductor die, the first stud bumps, and the bond wires in an encapsulation material; removing the carrier from the bottom side of the semiconductor package exposing a portion of the first stud bumps; and attaching one or more solder balls to the exposed portion of the first stud bumps.Type: GrantFiled: May 27, 2015Date of Patent: October 4, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Leo M. Higgins, III, Glenn G. Daves
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Patent number: 9461012Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.Type: GrantFiled: December 2, 2014Date of Patent: October 4, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Leo M. Higgins, III, Chu-Chung Lee
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Patent number: 9324667Abstract: A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.Type: GrantFiled: January 13, 2012Date of Patent: April 26, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Trent S. Uehling, Lawrence S. Klingbeil, Mostafa Vadipour, Brett P. Wilkerson, Leo M. Higgins, III