Abstract: A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.

Abstract: A process for fabricating an integrated circuit package. Metal is plated up on a substrate to provide a plurality of contact pads and a plurality of fiducial markings on a periphery of the contacts. A transparent mask is selectively deposited on the substrate, over the fiducial markings. A semiconductor die is mounted on the substrate such that the contact pads circumscribe the semiconductor die and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds are encapsulated and the semiconductor die and contact pads are covered in a molding material. The substrate is selectively etched to thereby etch away the substrate underneath the contact pads and the semiconductor die. The integrated circuit package is singulated from other integrated circuit packages by sawing using the fiducial markings.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A method and structure of ex-situ polymer stud grid array (ESWS-PSGA) contact formation on a semiconductor wafer having individual integrated circuit (IC) device areas. A large area of a polymer stud grid array (PSGA) field, including a polymer film, is pre-fabricated and then interconnected with the semiconductor wafer, and the ESWS-PSGA is formed using methods including laser structuring, compression molding, photolithographic-plasma etching, photolithographic processing, or adding material to the surface of the polymer film. The ESWS-PSGA has the PSGA field extend across the entire active surface of the semiconductor wafer, with metallized PSGA input/output (I/O) studs being disposed across the individual IC device areas. Alternatively, the ESWS-PSGA can be formed by spreading an extension of the polymer film beyond the perimeter of the semiconductor wafer, with metallized PSGA input/output (I/O) studs being disposed across the individual IC device areas.

Abstract: A interconnection circuit includes a dielectric plane having conductors fabricated from copper disposed on each side of the dielectric plane. An opening known as a via disposed through the dielectric plane includes a conductive link between the conductors disposed on either side of the dielectric plane. The conductive link includes a first layer fabricated from copper and a second layer of Nickel disposed over the copper layer to strengthen the first layer and prevent fractures known as barrel cracks in the conductive link. A third layer composed of Gold is deposited over the second layer to protect the second layer of Nickel from corrosion. In another embodiment of the subject invention the third layer is composed of an easily cleaned or removed metal and a coating of Gold is deposited in specific discrete locations to facilitate wire bonding or soldering.

Abstract: A system and method for the automated alignment and assembly of a first end of an optical fiber to an optical module includes a second optical module generally adjacent a second end of the optical fiber and connected to a computer. The computer monitors the optical transmission between the two modules through the optical fiber and controls movement of the first end of the optical fiber to optimize the position of the first end of the optical fiber relative to the first optical module.

Abstract: Methods and structures of in-situ wafer scale polymer stud grid array (ISWS-PSGA) contact formation on integrated circuit devices, wherein a separate pre-manufactured PSGA substrate is not needed. The methods include injection molding of thermoplastics, transfer-molding of thermoset materials, lamination of polymer films with subsequent in-situ molding/embossing, and forming the PSGA structure directly on the semiconductor wafer. The ISWS-PSGA structure extends across the entire semiconductor wafer, with ISWS-PSGA metallized input/output studs disposed across each of the integrated circuit devices on the wafer. The polymer formed on the wafer surface to create the stud field is extended beyond the perimeter of the wafer, and the polymer film extension is used for temporary connection to an integrated circuit tester, or an integrated circuit test/burn-in system. The extension may further include studs for contacting the tester.

Abstract: A semiconductor device (1) has a sub-chip-scale package structure, wherein the substrate (50) has at least one of an X dimension and a Y dimension smaller than a corresponding dimension of the semiconductor die (10). The semiconductor device (1) has a plurality of electrical connections between the semiconductor die and the substrate, the electrical connections (15, 20) being provided within the outer periphery of the substrate. The semiconductor device (1) permits packaging of semiconductor die (10) at the wafer level, that is, before the semiconductor die are singulated.

Abstract: A semiconductor device (1) has a sub-chip-scale package structure, wherein the substrate (50) has at least one of an X dimension and a Y dimension smaller than a corresponding dimension of the semiconductor die (10). The semiconductor device (1) has a plurality of electrical connections between the semiconductor die and the substrate, the electrical connections (15, 20) being provided within the outer periphery of the substrate. The semiconductor device (1) permits packaging of semiconductor die (10) at the wafer level, that is, before the semiconductor die are singulated.

Abstract: A flip-chip semiconductor device (70) is formed by mounting a semiconductor die (20) to a wiring substrate (30). The wiring substrate includes a hole (39). An underfill encapsulation material (52) is dispensed around an entire perimeter of the semiconductor die. The underfill encapsulation material then flows toward the center of the die, expelling any trapped air through hole (39) of the wiring substrate to avoid voiding. By providing a method which utilizes an entire perimeter dispense, manufacturing time of the underfilling step is significantly reduced. At the same time, a uniform fillet is formed and the formation of voids in the underfill encapsulation material is avoided due to the presence of hole (39) in the wiring substrate. Multiple die (100) can also be underfilled using a single dispensing operation in accordance with the invention.

Abstract: A TAB semiconductor device (98) is manufactured with a TAB tape (62') which provides an intrinsic standoff for the device. The tape (62') has a carrier film (66'), having at least one cavity, and a plurality of conductors (64) on the top surface of the carrier film. A semiconductor die (42) is substantially centered either inside or below the cavity in the film. The conductors overlie bonding sites (44) on the active surface of the die. Inner-lead-bonds are made between the conductors and the bonding sites, wherein the conductors bend at the edges (65') of the cavity in order to contact the bonding sites, thus concurrently achieving a downset during the action of bonding. An encapsulant (99) provides protection to the die, the inner-lead-bonds, and a portion of the conductors.

Abstract: Electronic components are shielded from electromagnetic interference (EMI) by one or more conformal layers filled with selected filler particulars for attenuate specific EMI frequencies or a general range of frequencies. Shielding is accomplished through the use of a single general purpose shielding layer, or through a series of shielding layers for protecting more specific EMI frequencies. In a multilayer embodiment, a semiconductor device (50) is mounted on a printed circuit board substrate (16) as a portion of an electronic component assembly (10). A conformal insulating coating (24) is applied over the device to provide electrical insulation of signal paths (e.g. leads 54 and conductive traces 18) from subsequently deposited conductive shielding layers. One or more shielding layers (60, 62, and 64) are deposited, and are in electrical contact with a ground ring (56).

Abstract: A semiconductor device (42) has a protective containment housing (44) around the edges (24) of the die (12) to protect the die. A plurality of leads (30) are TAB bonded to the die's active surface (18). The containment housing is attached around the die such that a portion of the inner sidewalls of the housing contacts the edges of the die to seal the edges. The top edge of the containment housing acts as a dam to prevent encapsulant (14') overflowing down the die edges and to the die's inactive surface (28). Various embodiments of the containment housing are possible.

Abstract: A semiconductor device (10) provides heat dissipation while maintaining a low profile. The device includes a circuitized substrate (12) having an opening (20). Inserted into, or at least covering, the opening is a heat sink (22) having a base portion (24), sidewalls (26), and flanges (28). Flanges of the heat sink are attached or supported by a surface of the substrate. Together the base portion and sidewalls of the heat sink form a cavity for receiving a semiconductor die (13). The die is electrically coupled to conductive traces (14) formed on the substrate by wire bonds (19), and the traces are electrically coupled to solder balls (21) by conductive vias (18). In one embodiment, base portion (24) of heat sink (22) extends below substrate (12) to permit contact to a user substrate (34). While in another embodiment, a base portion (118) of a heat sink (116) is exposed on a top surface of a substrate (112) for coupling to another heat sink (124).

Abstract: Conductive bumps (24) are formed on a semiconductor device (10) by applying or depositing an imageable conductive layer (18) over the device and in contact with I/O pads of a final metallization layer (14). The imageable conductive material is formed of an imageable acrylic resin system filled with conductive particles. In one embodiment, a mask (20) having a pattern of transparent material (21) corresponding to the desired patterned of conductive bumps is used to expose the imageable conductive layer to radiation (23). The imageable conductive layer is then developed, thereby removing unexposed portions of the layer and leaving a plurality of conductive bumps (24) on the I/O pads of the device. Rather than using a negatively imaged conductive layer, a positive resin could be used in formulating the imageable conductive material.

Abstract: An array type semiconductor device (10 and 40) has compliant polymer columnar I/O connections (30) to accommodate thermally induced stress during device operation. The device has a semiconductor die (22) mounted to a substrate (12) and electrically connected thereto. A package body (28, 46) covers the semiconductor die and electrical connections (26, 42) to provide mechanical protection. The I/O contacts are formed from a polymer core (34) that is metallized to impart electrical conductivity to the contacts. The metallization (36, 38) may either be a plating around the polymer core or fillers embedded in the polymer. The aspect ratio of the polymer contacts is greater than one to provide compliance while maintaining high I/O density in the array. The metallized polymer contacts may be attached to the package substrate and to a PWB with joints (32) composed of either solder or a conductive adhesive.

Abstract: A compliant integrated circuit (IC) wiring substrate (10) has an insulative carrier film (14) and a plurality of micro-beam conductors (12) in the carrier film. Each of the plurality of micro-beam conductors has a pair of contact bumps (16 and 18) connected to respective posts (22 and 24). A beam element (20) connects the pair of contact bumps and posts at opposing ends and opposing surfaces of the beam element. The plurality of micro-beam conductors extend through the thickness of the carrier film such that the pair of contact bumps protrude from the opposite surfaces of the carrier film. The compliance of the wiring substrate can be varied by varying locations of apertures in the insulative carrier film.

Abstract: A low cost method is used to standardize testing of bare semiconductor devices. In one embodiment, a universal test circuit substrate (10) having an interleaving fan-out pattern of conductive traces (14) is provided. The radial array of conductive traces terminates in a plurality of test pads (16) placed in a standard pattern around a periphery of a central die accommodating region. A die cavity (36), slightly larger than the size of a semiconductor die (32) to be tested, is formed in the central die accommodating region. The semiconductor die is placed approximately centered in the die cavity and is wire bonded (40) to individual traces of the pattern of conductive traces. The die can be tested and burned-in on the universal test circuit substrate with a test probe making contact with the test pads. The universal test circuit substrate can accommodate a multiplicity of die sizes and pin-out requirements of semiconductor devices.

Abstract: Deformation of TAB tapes due to temperature changes is prevented by thermo-mechanical leads. In one embodiment of the invention, a semiconductor device (30) includes an electronic component (31) and a TAB tape. The tape includes a carrier film (12) and electrical leads (20) formed on the carrier film. The electrical leads are electrically coupled to the electronic component. Also included on the carrier film are thermo-mechanical leads (32) which are formed in opposing regions of the carrier film, regions which are typically void of leads. The thermo-mechanical leads have approximately the same lead pitch as the electrical leads in order to provide a uniform distribution of stresses across the TAB tape upon exposure to varying temperatures.