Abstract: Described herein are compounds and pharmaceutical compositions containing such compounds, which inhibit the activity of Olig2. Also described herein are methods of using such Olig2 inhibitors, alone and in combination with other compounds, for treating cancer and other diseases. In particular the Olig2 inhibitors may be used to treat glioblastoma.

Abstract: Systems and methods for regulating weather information collection are provided. In one embodiment, a method for managing the collection of weather information comprises: determining whether or not a weather data processing system is in a state open to receiving weather information; communicating to a first aircraft when the weather data processing system is in a state open to receiving weather information; and upon receiving weather information at the weather data processing system from the first aircraft, transmitting a signal indicating that the weather data processing system is not in a state open to receiving weather information.

Abstract: Known lipid molecules of a matrix are grouped into lipid classes and the lipid classes are further grouped into a pass-through group and a mobility separation group based on isobaric interferences. A separation system separates known lipid molecules from a matrix sample and an ion source ionizes the matrix sample. Two injections are performed. For the first injection a DMS device is put into passive mode, and for the second injection the DMS device is used to resolve isobaric interferences. A tandem mass spectrometer performs MRM scans of the pass-through group for the first injection and MRM scans of the mobility separation group for the second injection. A processor quantitates each lipid molecule in the matrix sample by comparing the MRM intensity values obtained for the first and second injections to MRM intensity and concentration values for known standards of the known lipid molecules of the matrix.

Abstract: Systems and methods for collecting weather information for selected airspace regions are provided. In one embodiment, a method for collecting weather information for selected airspace regions comprises: receiving aircraft position information for a plurality of aircraft; forming an aircraft weather group based on flight path attributes derived from the aircraft position information; selecting at least a first representative aircraft from the weather group; and receiving at a weather information ground station, weather data from one or more representative aircraft of the aircraft weather group, wherein only the one or more representative aircraft transmit weather information to the weather information ground station from the aircraft weather group.

Abstract: Systems and methods for regulating weather information collection are provided. In one embodiment, a method for managing the collection of weather information comprises: determining whether or not a weather data processing system is in a state open to receiving weather information; communicating to a first aircraft when the weather data processing system is in a state open to receiving weather information; and upon receiving weather information at the weather data processing system from the first aircraft, transmitting a signal indicating that the weather data processing system is not in a state open to receiving weather information.

Abstract: Compounds which are glycosylates of an A-ring of a cardiotonic steroid, wherein the steroid is attached to the anomeric position of (a) a monosaccharide comprising a C-4 amino group, or (b) an oligosaccharide are provided.

Abstract: Meeting participants of a videoconference can be enabled to alert the other meeting participants that they are going to be away from or inattentive during a portion of the videoconference. For example, each meeting participant can be presented with a user interface element, such as a button, that the meeting participant can select to alert the other meeting participants that the meeting participant will be away or inattentive during a portion of the videoconference. The meeting participants can also be enabled to alert an away meeting participant to rejoin the videoconference. For example, meeting participants can be presented with a user interface element, such as a button, that can be selected to send an alert to an away meeting participant to rejoin the teleconference. A meeting participant can also select to be alerted when a specified alert trigger occurs, such as when a specified word or phrase is used.

Abstract: A self-contained breathing apparatus. The self-contained breathing apparatus comprises a back plate comprising a shoulder strap load portion and a waist belt load portion, wherein the waist belt load portion rotates about an extended axis defined by the junction of the waist belt load portion with the shoulder strap load portion, a shoulder strap coupled to the shoulder strap load portion of the back plate, a waist belt coupled to the waist belt load portion of the back plate, and a bottle of compressed breathable air secured to the shoulder strap load portion of the back plate.

Abstract: A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.

Abstract: A gazebo having four or more support columns connected together to form a frame structure which supports a covering support structure which in turn supports a roof covering has decorative posts (e.g., eight in number when four support columns are used) which are connected to the frame structure so that each support column is connected to two decorative posts, and each of the decorative posts has a replaceable top which can be an ornamental top, a bird feeder, a planter or a light, and the tops can be mix and matched, or identical tops can be used with all of the decorative posts, or some partial combination or grouped combination can be used, thus allowing for substantial customization opportunities. The decorative posts can have electrical connections running to connecting support columns, and all of the electrical connections can be connected together and connected to a solar energy source supported by the covering support structure.

Abstract: A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

Abstract: A manufacturing method of a flash memory cell is provided. The flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.

Abstract: A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

Abstract: A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

Abstract: A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are formed over the active region. A portion of each device isolation structure is removed to form a plurality of trenches. A dielectric layer is formed over the substrate and a sacrificial layer is filled the trenches. A portion of the dielectric layer is removed using the sacrificial layer as a self-aligned mask. The patterned mask layer is removed and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer and a control gate are formed over the substrate. A source region and a drain region are formed in the substrate on each side of the control gate.

Abstract: A flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.

Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.

Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.