Patents by Inventor Leonard Forbes

Leonard Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Split gate flash memory cell with ballistic injection
    Patent number: 7697328
    Abstract: A split floating gate flash memory cell includes source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: April 13, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Atomic layer deposited titanium silicon oxide films
    Patent number: 7687409
    Abstract: A dielectric layer containing an atomic layer deposited titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. Embodiments include forming titanium silicates and/or mixtures of titanium oxide and silicon oxides as dielectric layers in devices in an integrated circuit. In an embodiment, a titanium silicon oxide film is formed by depositing titanium oxide by atomic layer deposition and silicon oxide by atomic layer deposition onto a substrate surface. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited titanium silicon oxide film, and methods for forming such structures.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
    Patent number: 7687329
    Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Memory utilizing oxide-conductor nanolaminates
    Patent number: 7687848
    Abstract: Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Ballistic direct injection NROM cell on strained silicon structures
    Patent number: 7683424
    Abstract: A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the silicon-germanium layer such that the pair of source/drain regions is linked by a channel that is generated in the strained silicon layer during operation of the cell. A nitride layer is formed overlying the substrate. The nitride layer has at least one charge storage region. The nitride layer may be a planar layer, a planar split gate nitride layer, or a vertical split nitride layer. A control gate is formed overlying the nitride layer. Ballistic direct injection is used to program the memory cell. A first charge storage region of the nitride layer establishes a virtual source/drain region in the channel. The virtual source/drain region has a lower threshold voltage than the remaining portion of the channel.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS
    Publication number: 20100067304
    Abstract: Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The MOSFET can be programmed by operation in a reverse direction trapping charge in the gate insulator adjacent to the first source/drain region such that the programmed MOSFET operates at reduced drain source current when read in a forward direction.
    Type: Application
    Filed: November 20, 2009
    Publication date: March 18, 2010
    Inventor: Leonard Forbes
  • Vertical transistor, memory cell, device, system and method of forming same
    Patent number: 7679118
    Abstract: A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Metal-substituted transistor gates
    Patent number: 7674698
    Abstract: One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors is formed. For each transistor, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. At least two substitution processes are performed. Each substitution process includes substituting a desired gate material for the substitutable structure. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: March 9, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Paul A. Farrar, Kie Y. Ahn
  • LANTHANIDE YTTRIUM ALUMINUM OXIDE DIELECTRIC FILMS
    Publication number: 20100052033
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by atomic layer deposition.
    Type: Application
    Filed: November 9, 2009
    Publication date: March 4, 2010
    Inventors: Kie Y. Ahn, Leonard Forbes
  • MEMORY IN LOGIC CELL
    Publication number: 20100055871
    Abstract: Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.
    Type: Application
    Filed: November 10, 2009
    Publication date: March 4, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hussein I. Hanafi, Leonard Forbes, Alan R. Reinberg
  • Methods for atomic-layer deposition
    Patent number: 7670646
    Abstract: Atomic-Layer deposition systems and methods provide a variety of electronic products. In an embodiment, a method uses an atomic-layer deposition system that includes an outer chamber, a substrate holder, and a gas-distribution fixture that engages or cooperates with the substrate holder to form an inner chamber within the outer chamber. The inner chamber has a smaller volume than the outer chamber, which leads to less time to fill and purge during cycle times for deposition of materials.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: March 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Non-planar flash memory array with shielded floating gates on silicon mesas
    Patent number: 7672171
    Abstract: A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. Wordlines couple rows of memory cells of the array. Metal shields are formed between adjacent wordlines and substantially parallel to the wordlines to shield the floating gates of adjacent cells.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: March 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
    Patent number: 7670469
    Abstract: In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Zr-Sn-Ti-O FILMS
    Publication number: 20100044771
    Abstract: A dielectric layer containing a Zr—Sn—Ti—O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. In an embodiment, forming the Zr—Sn—Ti—O film on a substrate includes depositing materials of the Zr—Sn—Ti—O film substantially as atomic monolayers. In an embodiment, electronic devices include a dielectric layer having a Zr—Sn—Ti—O film such that Zr—Sn—Ti—O material is configured as substantially atomic monolayers. Dielectric layers containing such Zr—Sn—Ti—O films may have minimal reactions with a silicon substrate or other structures during processing.
    Type: Application
    Filed: October 30, 2009
    Publication date: February 25, 2010
    Inventors: Kie Y. Ahn, Leonard Forbes
  • HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC
    Publication number: 20100041244
    Abstract: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 18, 2010
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
    Patent number: 7662729
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a conductive layer having a layer of ruthenium in contact with a lanthanide oxide dielectric layer for use in a variety of electronic systems. The lanthanide oxide dielectric layer and the layer of ruthenium may be structured as one or more monolayers. The lanthanide oxide dielectric layer and the layer of ruthenium may be formed by atomic layer deposition.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
    Patent number: 7662701
    Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • HAFNIUM TANTALUM OXIDE DIELECTRICS
    Publication number: 20100029054
    Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.
    Type: Application
    Filed: October 12, 2009
    Publication date: February 4, 2010
    Inventors: Kie Y. Ahn, Leonard Forbes
  • ERASABLE NON-VOLATILE MEMORY DEVICE USING HOLE TRAPPING IN HIGH-K DIELECTRICS
    Publication number: 20100027345
    Abstract: A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K.
    Type: Application
    Filed: October 12, 2009
    Publication date: February 4, 2010
    Inventors: Leonard Forbes, Kie Y. Ahn
  • ZINC OXIDE DIODES FOR OPTICAL INTERCONNECTIONS
    Publication number: 20100014805
    Abstract: The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has an input coupled to the ZnO emitter. A detector is coupled to an output of the optical waveguide.
    Type: Application
    Filed: September 23, 2009
    Publication date: January 21, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Leonard Forbes, Kie Y. Ahn