Patents by Inventor Lester Lampert
Lester Lampert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11177912Abstract: One aspect of the present disclosure provides a quantum circuit assembly that includes a substrate with one or more qubit devices, and at least one demultiplexer included in a single chip with the qubit device(s). The demultiplexer is configured to receive a combined signal from external electronics, the combined signal including a combination of a plurality of signals in different frequency ranges, and to demultiplex said plurality of signals within the combined signal. The demultiplexer is further configured to apply different demultiplexed signals to different lines of a single qubit device, or/and to different qubit devices. Providing such demultiplexers on-chip with the qubit devices advantageously allows reducing the number of input/output lines coupling the chip with qubit devices and the external electronics.Type: GrantFiled: March 6, 2018Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Adel A. Elsherbini, Javier A. Falcon, Lester Lampert
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Publication number: 20210328019Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Applicant: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Patent number: 11114530Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: GrantFiled: December 17, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Patent number: 11011693Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.Type: GrantFiled: June 24, 2019Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Thomas Francis Watson, Stephanie A. Bojarski, James S. Clarke
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Publication number: 20210066570Abstract: Embodiments of the present disclosure describe quantum circuit assemblies that include one or more filter modules integrated in a package with a quantum circuit component having at least one qubit device. Integration may be such that both the quantum circuit component and the filter module(s) are at least partially inside a chamber formed by a radiation shield structure that is configured to attenuate electromagnetic radiation incident on the quantum circuit component and the filter module(s). Placing filter modules under the protection provided by the radiation shield structure may boost coherence of the qubits. Some example filter modules may include filter(s) configured to convert electromagnetic radiation to heat and filter(s) configured to perform bandpass filtering. Modular blocks of in-line filters inside the shielded environment may allow to route signals to the quantum circuit component with reduced noise and speed up installation of a complete quantum computer.Type: ApplicationFiled: September 4, 2019Publication date: March 4, 2021Applicant: Intel CorporationInventors: Florian Luethi, Lester Lampert
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Publication number: 20210036110Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: ApplicationFiled: December 17, 2017Publication date: February 4, 2021Applicant: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Patent number: 10910488Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin has a first side face and a second side face, and the fin includes a quantum well layer; and a gate above the fin, wherein the gate extends down along the first side face.Type: GrantFiled: June 26, 2018Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Hubert C. George, Lester Lampert, James S. Clarke, Ravi Pillarisetty, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
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Patent number: 10899938Abstract: Disclosed embodiments concern a composition comprising a diatom frustule and two or more photocatalytic nanoparticles dispersed on the surface of the frustule. Also disclosed are embodiments of a method for making the composition. The nanoparticles are dispersed such that they are separate and not in physical contact with each other. An average distance between the nanoparticles may be from greater than 0 nm to 100 nm. The nanoparticles may comprise a dopant material. Paint compositions comprising the diatom frustule compositions are also contemplated. The diatom frustule composition may be useful for removing and/or degrading volatile organic compounds, such as those present in the atmosphere.Type: GrantFiled: June 6, 2019Date of Patent: January 26, 2021Assignee: Portland State UniversityInventors: Lester Lampert, Haiyan Li
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Patent number: 10879446Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.Type: GrantFiled: August 14, 2018Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Roman Caudillo, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke
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Publication number: 20200403137Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.Type: ApplicationFiled: June 24, 2019Publication date: December 24, 2020Inventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Thomas Francis Watson, Stephanie A. Bojarski, James S. Clarke
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Publication number: 20200373351Abstract: Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.Type: ApplicationFiled: September 18, 2017Publication date: November 26, 2020Applicant: Intel CorporationInventors: Jeanette M. Roberts, Wesley T. Harrison, Adel A. Elsherbini, Stefano Pellerano, Zachary R. Yoscovits, Lester Lampert, Ravi Pillarisetty, Roman Caudillo, Hubert C. George, Nicole K. Thomas, David J. Michalak, Kanwaljit Singh, James S. Clarke
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Patent number: 10847705Abstract: Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.Type: GrantFiled: February 15, 2018Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Lester Lampert, Adel A. Elsherbini, James S. Clarke, Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Kanwaljit Singh, Roman Caudillo, Zachary R. Yoscovits, Nicole K. Thomas, Hubert C. George, Stefano Pellerano
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Patent number: 10803396Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.Type: GrantFiled: June 19, 2018Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Zachary R. Yoscovits, Roman Caudillo, Ravi Pillarisetty, Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Nicole K. Thomas, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
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Publication number: 20200312963Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Stephanie A. Bojarski, Hubert C. George, Sarah Atanasov, Nicole K. Thomas, Ravi Pillarisetty, Lester Lampert, Thomas Francis Watson, David J. Michalak, Roman Caudillo, Jeanette M. Roberts, James S. Clarke
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Publication number: 20200312989Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.Type: ApplicationFiled: March 26, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Hubert C. George, Sarah Atanasov, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts, Stephanie A. Bojarski
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Publication number: 20200295164Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a first gate above the quantum well stack, wherein the first gate includes a first gate metal; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal, and a material structure of the second gate metal is different from a material structure of the first gate metal; wherein the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.Type: ApplicationFiled: January 8, 2018Publication date: September 17, 2020Applicant: Intel CorporationInventors: Kanwaljit Singh, Ravi Pillarisetty, Nicole K. Thomas, Payam Amin, Roman Caudillo, Hubert C. George, Jeanette M. Roberts, Zachary R. Yoscovits, James S. Clarke, Lester Lampert, David J. Michalak
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Publication number: 20200258984Abstract: Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Applicant: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Stephanie A. Bojarski, Roman Caudillo, David J. Michalak, Jeanette M. Roberts, Thomas Francis Watson
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Patent number: 10714604Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.Type: GrantFiled: June 25, 2018Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Hubert C. George, David J. Michalak, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, Jeanette M. Roberts
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Patent number: 10686007Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.Type: GrantFiled: June 20, 2018Date of Patent: June 16, 2020Assignee: Intel CorporationInventors: Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Ravi Pillarisetty, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
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Patent number: 10665769Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.Type: GrantFiled: June 19, 2018Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Roman Caudillo, Zachary R. Yoscovits, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke