Abstract: It is provided a driving system, a driving method, a computer system and a computer readable medium. The driving system includes: an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjusting circuit configured to automatically detect a present amplitude of the on-chip voltage output by the input circuit and to output a bias voltage corresponding to the present amplitude of the on-chip voltage to a gate of the driven thin film transistor, wherein a source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage. The protection of the transistor gate and the adjusting of a receiver threshold voltage for different I/O (input/output) voltages and levels can be completed through automatic detection of the on-chip voltage and automatic adjusting.

Abstract: An ultrasonic transducer includes an elongated transducer body with an aperture for mounting a piezoelectric driver stack for driving the ultrasonic transducer to operate at a first resonant frequency, a mounting flange for mounting the transducer body to a wire bonding machine, a rigid connecting member having first and second ends which are respectively connected to the mounting flange and the transducer body at a first nodal vibration region of the transducer body when the ultrasonic transducer is operated at the first resonant frequency and a flexible connecting member extending between the mounting flange and the transducer body at a second nodal vibration region of the transducer body when the ultrasonic transducer is operated at the first resonant frequency.

Abstract: An ultrasonic transducer that is configured to selectively operate at first or second resonant frequency during wire bonding operations includes an elongated transducer body an aperture for mounting a piezoelectric driver stack for driving the ultrasonic transducer to operate at the first or second resonant frequency and a mounting flange connected to the transducer body at a first nodal vibration region of the transducer body when the ultrasonic transducer is operated at the first resonant frequency. The elongated transducer has a length substantially equal to two wavelengths of a first oscillatory wave that is transmitted along the length of the transducer body when the transducer is operated at the first resonant frequency, and substantially equal to a half wavelength of a second oscillatory wave that is transmitted along the length of the transducer body when the transducer is operated at the second resonant frequency.

Abstract: It is provided a driving system, a driving method, a computer system and a computer readable medium. The driving system includes: an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjusting circuit configured to automatically detect a present amplitude of the on-chip voltage output by the input circuit and to output a bias voltage corresponding to the present amplitude of the on-chip voltage to a gate of the driven thin film transistor, wherein a source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage. The protection of the transistor gate and the adjusting of a receiver threshold voltage for different I/O (input/output) voltages and levels can be completed through automatic detection of the on-chip voltage and automatic adjusting.

Abstract: An obstacle detection system includes a light emitter that emits a light signal and a light detector configured to receive a portion of the light signal reflected back from an object. The system includes a processor operatively coupled to the light emitter and the light detector to determine a presence of an obstacle based on the portion of the light signal received by the light detector. The system includes a heater operatively coupled to a power source and at least one sensor configured to determine an ambient temperature and an ambient relative humidity. The processor is operatively coupled to the power source, the heater, and the at least one sensor. The processor is configured to calculate a dew point of the environment from the ambient relative humidity and the ambient temperature and to activate the heater in response to the ambient temperature being less than the dew point.

Abstract: An obstacle detection system includes a light emitter that emits a light signal and a light detector configured to receive a portion of the light signal reflected back from an object. The system includes a processor operatively coupled to the light emitter and the light detector to determine a presence of an obstacle based on the portion of the light signal received by the light detector. The system includes a heater operatively coupled to a power source and at least one sensor configured to determine an ambient temperature and an ambient relative humidity. The processor is operatively coupled to the power source, the heater, and the at least one sensor. The processor is configured to calculate a dew point of the environment from the ambient relative humidity and the ambient temperature and to activate the heater in response to the ambient temperature being less than the dew point.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: A system and method for receiving input from a user is provided. The system includes at least one camera configured to receive an image of a hand of the user and a controller configured to analyze the image and issue a command based on the analysis of the image.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: A system and method for receiving input from a user is provided. The system includes at least one camera configured to receive an image of a hand of the user and a controller configured to analyze the image and issue a command based on the analysis of the image.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: In one implementation, voice service discovery may include a voice service discovery protocol (VSDP) and a VSDP device, which receives voice virtual local area network data and generates a packet including root voice service configuration data. The VSDP device may be in an enabled state, a listening state, or a disabled state. Receiving voice service configuration data may initiate the enabled state in the VSDP device, and the packet may be transmitted to a remote device. Voice service discovery may include advertising a voice service to a plurality of voice over internet protocol endpoints according to the root voice service configuration data.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.