Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: A data receiver includes group envelope detection circuitry that produces a group envelope voltage. The group envelope voltage represents the average envelope of a plurality of amplified data signals. Associated feedback adjusts the gains applied to each data signal to minimize any difference between the group envelope voltage and a reference voltage. The reference voltage is preferably the envelope of a clock signal associated with the data signals.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Abstract: A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. A reference clock signal is propagated along a source path and a return path, both of which pass near the registers. At each register, an averaged clock signal is generated, based on the phases of the reference clock signal on the source and return paths. Individual component clock signals are then adjusted separately to minimize differences between the component clock signals and the respective averaged clock signals at each of the registers.

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.

Abstract: A data receiver includes group envelope detection circuitry that produces a group envelope voltage. The group envelope voltage represents the average envelope of a plurality of amplified data signals. Associated feedback adjusts the gains applied to each data signal to minimize any difference between the group envelope voltage and a reference voltage. The reference voltage is preferably the envelope of a clock signal associated with the data signals.

Abstract: A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.