Abstract: An intrusion detection and prevention system (IDPS) has detection probes and detection hubs that are deployed onboard a connected vehicle and a detection correlation backend that is deployed on the cloud. A detection probe receives raw packets of network traffic of a communication network of the connected vehicle. The detection probe filters the raw packets in accordance with packet filter rule entries to generate packets of interest. The detection probe scans the packets of interest for data indicative of network threats and outputs corresponding unfiltered detection logs. The detection probe filters the unfiltered detection logs in accordance with detection filter rule entries to generate detection logs of interest. A detection hub aggregates detection logs of interest from one or more detection probes to generate aggregated detection logs. A detection correlation backend evaluates the aggregated detection logs to detect network threats.

Abstract: A semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.

Abstract: Some implementations described herein provide a semiconductor device including a trench capacitor structure and methods of forming. Using a multi-electrode connection that includes use of a conductive sidewall layer, an interconnect structure may connect with multiple, vertically-arranged electrode layers of the trench capacitor structure. In contrast to connecting with a single electrode layer, connecting with the multiple, vertically-arranged electrode layers may increase an effective thickness of a land for the interconnect structure. The increased effective thickness may reduce a likelihood of vertical interconnect access island corrosion defects developing in metal structures of the trench capacitor structure.

Abstract: Disclosed are a food grade starch based modeling clay with high elasticity and high ductility and its preparation method, belonging to the technical field of modeling clay preparation. The starch based modeling clay provided by the present disclosure is prepared from the following formula components: 160-180 parts of starch, 140-160 parts of water, 10-15 parts of a food grade stabilizer, 10-15 parts of edible salt, 0-10 parts of hydrophilic colloid, 0.6-0.8 parts of a preservative, 40-60 parts of a food grade plasticizer, 6-10 parts of food grade white oil, and 4-8 parts of edible pigment. The starch includes one or a combination of more of cassava starch, wheat starch, and glutinous rice starch. The present disclosure, through combined use of the starch and the hydrophilic colloid, makes the prepared starch based modeling clay have good viscoelasticity and ductility, and good in storage stability, safe and non-toxic.

Abstract: An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: Some implementations described herein include a semiconductor device including a thin film resistor structure and techniques for forming the thin film resistor structure. Techniques described herein include forming a layer of a resistive material using a dual-component physical vapor deposition process and forming contact structures on the layer of resistive material by directly patterning a layer of conductive material on the layer of the resistive material. The techniques further include oxidizing a surface of the layer of the resistive material between the contact structures.

Abstract: A semiconductor structure includes a semiconductor substrate, a serpentine-shaped resistor, and a MOS transistor. The semiconductor substrate includes an isolation structure and an active region. The serpentine-shaped resistor is over the isolation structure. The serpentine-shaped resistor extends in a length direction and has a width that is equal to or greater than about 3.6 ?m in a width direction. The MOS transistor is over the active region of the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor structure is disclosed. The method includes the following operations. An insulation region is formed in a substrate to define an active region in the substrate. A gate structure is formed across the active region. A source or drain region is formed in the active region and adjoins the insulation region. A resist protective dielectric film is formed, wherein the resist protective dielectric film overlaps an interface between the source or drain region and the insulation region, and exposes a portion of the source or drain region and a portion of the gate structure.

Abstract: A control method, for controlling a reading operation of a memory device, includes the following steps. A toggle signal is provided to the memory device, and the toggle signal has a toggle frequency. A reading operation of a page of the memory device is performed according to the toggle signal, wherein the page includes a plurality of chunks. The toggle frequency is set as a target toggle frequency, and the reading operation of a first chunk of the page is performed according to the target toggle frequency, so as to receive a data signal of the memory device. After the reading operation of the first chunk is completed, the toggle frequency is selectively adjusted to perform the reading operation of a second chunk after the first chunk according to a stable state of the data signal and the data strobe signal.

Abstract: An object detection system of a vehicle includes a camera and a LIDAR sensor. The camera and the LIDAR sensor sense an environment to generate an image and a point cloud that depict the environment. The image and point cloud are preprocessed to facilitate comparison between the image and the point cloud. Similarity between the image and the point cloud in depicting the environment is determined to detect abnormal sensor data. Abnormal sensor data is further detected based on directional pattern strengths of edges of the image and expanded points of the point cloud. Detected abnormal sensor data in the image and point cloud are filtered to generate a secure image and a secure point cloud, which are provided to a perception engine to detect objects or other features in the environment.

Abstract: Systems and techniques are provided for generating a texture for a three-dimensional (3D) facial model. For example, a process can include obtaining a first frame, the first frame including a first portion of a face. In some aspects, the process can include generating a 3D facial model based on the first frame and generating a first facial feature corresponding to the first portion of the face. In some examples, the process includes obtaining a second frame, the second frame including a second portion of the face. In some cases, the second portion of the face at least partially overlaps the first portion of the face. In some examples, the process includes combining the first facial feature with the second facial feature to generate an enhanced facial feature, wherein the combining is performed to enhance an appearance of select areas of the enhanced facial feature.

Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N stack, where 0<x1?1 and 0?y1<1. An LED device including the multi-quantum well structure is also disclosed.

Abstract: Embodiments of the present disclosure provide an asset information collection method, an electronic device, and a computer-readable storage medium. The telecommunication asset information collection method includes: configuring collection parameters including collection time and collection point information; in a case of arrival of the collection time, generating a collection task according to the collection point information; acquiring collected data from a collection point corresponding to the collection point information according to the collection task, with the collected data including: asset information and asset association relationship information; and generating an information processing task, and constructing an asset association relationship map according to the information processing task and the collected data and storing the constructed asset association relationship map, or updating a stored asset association relationship map according to the information processing task and the collected data.

Abstract: A 4 frequency-shift keying (4FSK) transceiver is provided. The 4FSK transceiver includes both a 4FSK transmitter and a 4FSK receiver. The 4FSK transmitter includes a voltage-controlled oscillator (VCO) and two data links coupled to the VCO for delivering two parallel streams of input data bits to the VCO. For each pair of parallel input data bits received from the two data links, the VCO outputs a modulated signal having one of four operating frequencies via 4FSK modulation. Separately, the 4FSK receiver includes a power divider, for dividing the multi-frequency modulated signal into two paths of two binary bit streams, and a pair of low-noise amplifiers (LNAs) separately coupled to the two paths and configured as a pair of band-pass filters for filtering two different subsets of the four operating frequencies from the two binary bit streams into two filtered binary bit streams.

Abstract: A semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.

Abstract: A device includes a memory and one or more processors configured to process sensor data to determine a semantical context associated with the sensor data. The one or more processors are also configured to generate adjusted face data based on the determined semantical context and face data. The adjusted face data includes an avatar facial expression that corresponds to the semantical context.

Abstract: A low friction horizontal probing fixture includes two rails of a base unit and two slide units respectively disposed on and being slidable along the rails. Each slide unit has a slide seat that is disposed adjacent to a respective one of the rails, rolling members that are connected to the slide seat and that are rollable on the respective rail so that the slide seat is movable along the respective rail, and a lock mechanism that is disposed on the slide seat and that is operable to position the slide seat relative to the respective rail. A guiding member is connected co-movably to the slide units.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.