Patents by Inventor Li-Chieh Hsu
Li-Chieh Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12210295Abstract: Some implementations described herein provide a reticle cleaning device and a method of use. The reticle cleaning device includes a support member configured for extension toward a reticle within an extreme ultraviolet lithography tool. The reticle cleaning device also includes a contact surface disposed at an end of the support member and configured to bond to particles contacted by the contact surface. The reticle cleaning device further includes a stress sensor configured to measure an amount of stress applied to the support member at the contact surface. During a cleaning operation in which the contact surface is moving toward the reticle, the stress sensor may provide an indication that the amount of stress applied to the support member satisfies a threshold. Based on satisfying the threshold, movement of the contact surface and/or the support member toward the reticle ceases to avoid damaging the reticle.Type: GrantFiled: April 28, 2023Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Chang Hsu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
-
Patent number: 10722998Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.Type: GrantFiled: September 28, 2017Date of Patent: July 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Kun-Ju Li, Po-Cheng Huang, Chun-Liang Liu
-
Publication number: 20200111802Abstract: A method of preventing charge loss from a floating gate includes providing a substrate comprising a memory cell region and a logic region, wherein a floating gate is disposed in the memory cell region and a gate structure is disposed within the logic region, a first hard mask covers the floating gate and a second hard mask covers the first hard mask. A planarization process is performed to remove entirely the second hard mask and expose the first hard mask. Later, a third hard mask is formed to cover the first hard mask, the gate structure and the substrate, wherein the third hard mask prevents charges in the floating gate from flowing to the first hard mask. Finally, the third hard mask within the logic region is removed and the third hard mask remains within the memory region.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Nan-Yuan Huang, Cheng-Lin Peng, Lung-En Kuo, Li-Chieh Hsu
-
Publication number: 20190070706Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.Type: ApplicationFiled: September 28, 2017Publication date: March 7, 2019Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Kun-Ju Li, Po-Cheng Huang, Chun-Liang Liu
-
Patent number: 10192826Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.Type: GrantFiled: December 26, 2017Date of Patent: January 29, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
-
Patent number: 10103034Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.Type: GrantFiled: August 16, 2017Date of Patent: October 16, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
-
Patent number: 10049887Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.Type: GrantFiled: August 16, 2017Date of Patent: August 14, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
-
Publication number: 20180138125Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.Type: ApplicationFiled: December 26, 2017Publication date: May 17, 2018Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
-
Patent number: 9972498Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.Type: GrantFiled: March 27, 2016Date of Patent: May 15, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yu-Ting Li, Chih-Hsun Lin, Li-Chieh Hsu, Yi-Liang Liu, Po-Cheng Huang, Kun-Ju Li, Wen-Chin Lin
-
Patent number: 9966263Abstract: A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.Type: GrantFiled: May 4, 2017Date of Patent: May 8, 2018Assignee: United Microelectronics Corp.Inventors: Kun-Ju Li, Li-Chieh Hsu, Yi-Han Liao, Chun-Tsen Lu, Chih-Hsun Lin, Hsin-Jung Liu
-
Publication number: 20180061656Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.Type: ApplicationFiled: August 24, 2016Publication date: March 1, 2018Inventors: Fu-Shou Tsai, Yu-Ting Li, Li-Chieh Hsu, Yi-Liang Liu, Kun-Ju Li, Po-Cheng Huang, Chien-Nan Lin
-
Patent number: 9905430Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.Type: GrantFiled: August 24, 2016Date of Patent: February 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yu-Ting Li, Li-Chieh Hsu, Yi-Liang Liu, Kun-Ju Li, Po-Cheng Huang, Chien-Nan Lin
-
Patent number: 9887158Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.Type: GrantFiled: November 2, 2016Date of Patent: February 6, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
-
Publication number: 20180033636Abstract: A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. A second layer covering the first layer is formed wherein the materials of the first layer and the second layer are different. A first polishing operation is performed on the second layer until a first polished surface exposing a portion of the first layer is obtained. A second polishing operation is performed on the first polished surface to obtain a second polished surface wherein an upper portion of the exposed portion of the first layer is removed. None of the substrate is exposed from the first polished surface and the second polished surface.Type: ApplicationFiled: July 27, 2016Publication date: February 1, 2018Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Po-Cheng Huang, Yi-Liang Liu, Wen-Chin Lin, Chun-Yi Wang, Chun-Yuan Wu
-
Publication number: 20180033633Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.Type: ApplicationFiled: July 26, 2016Publication date: February 1, 2018Inventors: Fu-Shou Tsai, Yu-Ting Li, Li-Chieh Hsu, Yi-Liang Liu, Kun-Ju Li, Po-Cheng Huang, Chien-Nan Lin
-
Patent number: 9875909Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.Type: GrantFiled: July 26, 2016Date of Patent: January 23, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yu-Ting Li, Li-Chieh Hsu, Yi-Liang Liu, Kun-Ju Li, Po-Cheng Huang, Chien-Nan Lin
-
Publication number: 20180012772Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.Type: ApplicationFiled: August 16, 2017Publication date: January 11, 2018Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
-
Publication number: 20180012771Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.Type: ApplicationFiled: August 16, 2017Publication date: January 11, 2018Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
-
Patent number: 9773682Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.Type: GrantFiled: July 5, 2016Date of Patent: September 26, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
-
Patent number: 9748147Abstract: A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.Type: GrantFiled: July 20, 2016Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Li-Wei Feng, Li-Chieh Hsu, Chun-Jen Chen, I-Cheng Hu, Tien-I Wu, Yu-Shu Lin, Neng-Hui Yang