METHOD OF PREVENTING CHARGE LOSS FROM A FLOATING GATE
A method of preventing charge loss from a floating gate includes providing a substrate comprising a memory cell region and a logic region, wherein a floating gate is disposed in the memory cell region and a gate structure is disposed within the logic region, a first hard mask covers the floating gate and a second hard mask covers the first hard mask. A planarization process is performed to remove entirely the second hard mask and expose the first hard mask. Later, a third hard mask is formed to cover the first hard mask, the gate structure and the substrate, wherein the third hard mask prevents charges in the floating gate from flowing to the first hard mask. Finally, the third hard mask within the logic region is removed and the third hard mask remains within the memory region.
The present invention relates to a method of preventing charge loss in a floating gate, and more particularly to a method of replacing a hard mask on a floating gate to prevent charge loss in the floating gate.
2. Description of the Prior ArtNonvolatile memory cell arrays such as EPROMs, FLASH EPROMs and EEPROMs have gained widespread acceptance in the industry. Nonvolatile memory cells do not require periodic refresh pulses, unlike DRAM cells.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
During a standard programming operation of a flash memory cell, a selected word line coupled to the selected memory cell to be programmed is biased with a series of incrementing voltage programming pulses that start at an initial voltage that is greater than a predetermined programming voltage. The programming pulse increase in charge level, thereby increasing the cell's threshold voltage Vt, on a floating gate of the memory cell.
It has been observed, however, that there are delays in charging and discharging of a flash because the electrons in the floating gate are trapped by the other material layers.
SUMMARY OF THE INVENTIONAccording to a preferred embodiment of the present invention, a method of preventing charge loss from a floating gate, includes providing a substrate comprising a memory cell region and a logic region, wherein a floating gate is disposed in the memory cell region and a gate structure is disposed within the logic region, a first hard mask covers the floating gate and a second hard mask covers the first hard mask. A planarization process is performed to remove entirely the second hard mask and expose the first hard mask. Later, a third hard mask is formed to cover the first hard mask, the gate structure and the substrate, wherein the third hard mask prevents charges in the floating gate from flowing to the first hard mask. Finally, the third hard mask within the logic region is removed and only the third hard mask within the memory cell region remains.
By replacing the second hard mask covering the floating gate with the third hard mask, the electron charges can remain in the floating gate instead of being trapped by the first hard mask.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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A gate structure 24 is disposed in the logic region B. Two source/drain doped regions 26 are disposed in the substrate 10 at two sides of the gate structure 24. The gate structure 24 includes a gate 28 and a dielectric layer 30 disposed on the gate 28. The gate 28 may be formed by polysilicon, metal or other conductive materials. A cap layer 32 is disposed on the gate structure 24. The cap layer 32 may be silicon oxide, silicon nitride or the combination thereof.
The gate structure 24 and the two source/drain doped regions 26 forma MOS transistor 34. Although there is only one MOS transistor 34 shown in the figure, the number of the MOS transistors 34 can be adjusted based on different requirements. The gate 28 may be polysilicon. The dielectric layer 30 may be silicon oxide, silicon oxynitride (SiON), silicon nitride (Si3N4), or any combination thereof. The dielectric layer 30 is preferably silicon oxide. The dielectric layer 30 extends to the memory cell region A and covers the floating gate 18. Furthermore, a first hard mask 36, a second hard mask 38, a first sacrificial layer 40 and a second sacrificial layer 42 cover the dielectric layer 30 in the memory cell region A. The first hard mask 36 is preferably silicon nitride. The second hard mask 38 is preferably silicon oxide. The first sacrificial layer 40 is preferably silicon nitride. The second sacrificial layer 42 is preferably silicon oxide.
The first hard mask 36, the second hard mask 38, the first sacrificial layer 40 and the second sacrificial layer 42 are arranged from bottom to top. For the sake of clarity, the first hard mask 36, the second hard mask 38, the first sacrificial layer 40 and the second sacrificial layer 42 are omitted in
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A conventional memory cell has a problem where the electrical charges stored in the floating gates are inclined to cross the dielectric layer and flow into the first hard mask. Eventually, the electrical charges originally in the floating gate are trapped in the first hard mask. Electron charges trapped in the first hard mask may elongate charge-discharge times of the memory cell. The present invention replaces the second hard mask originally on the first hard mask with the third hard mask. The third hard mask decreases the trapping ability of the first hard mask, and the electrical charges can be kept in the floating gates.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1: A method of preventing charge loss from a floating gate, comprising:
- providing a substrate comprising a memory cell region and a logic region, wherein the floating gate is disposed in the memory cell region and a gate structure is disposed within the logic region, a first hard mask covers the floating gate and a second hard mask covers the first hard mask;
- performing a planarization process to remove entirely the second hard mask and expose the first hard mask;
- forming a third hard mask to cover the first hard mask, the gate structure and the substrate, wherein the third hard mask prevents charges in the floating gate from flowing to the first hard mask; and
- removing the third hard mask within the logic region while the third hard mask remains within the memory cell region.
2: The method of preventing charge loss from the floating gate of claim 1, wherein the first hard mask is silicon nitride and the second hard mask is silicon oxide.
3: The method of preventing charge loss from the floating gate of claim 1, wherein the third hard mask comprises silicon oxide, silicon oxycarbonitride (SiOCN) or silicon oxynitride (SiON).
4: The method of preventing charge loss from the floating gate of claim 1, wherein a thickness of the second hard mask equals a thickness of the third hard mask.
5: The method of preventing charge loss from the floating gate of claim 1, wherein a thickness of the third hard mask is smaller than twice a thickness of the second hard mask.
6: The method of preventing charge loss from the floating gate of claim 1, wherein an erase gate is disposed at a side of the floating gate, and after removing the third hard mask within the logic region, simultaneously forming contact plugs which respectively contact the gate structure and the erase gate.
Type: Application
Filed: Oct 4, 2018
Publication Date: Apr 9, 2020
Inventors: Nan-Yuan Huang (Tainan City), Cheng-Lin Peng (Tainan City), Lung-En Kuo (Tainan City), Li-Chieh Hsu (Taichung City)
Application Number: 16/152,368