Patents by Inventor Li Fan

Li Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electrostatic discharge protection circuit
    Patent number: 10784252
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
  • VEHICLE CHASSIS
    Publication number: 20200239078
    Abstract: A vehicle chassis including a vehicle frame defining an inner space and being operable to switch between a first expanded state and a collapsed state, and a loading device mounted to the inner space and removably connected to the vehicle frame. The loading device defines a first loading surface when the vehicle frame is in the first expanded state, and the loading device defines a second loading surface that is smaller than the first loading surface when the vehicle frame is in the collapsed state.
    Type: Application
    Filed: November 13, 2019
    Publication date: July 30, 2020
    Applicant: National Taiwan Normal University
    Inventors: Yi-Hsuan HUNG, Ping-Hung SHIH, Li-Fan LIU, Yi-Ya LIAO, Kan-Yuan TIAN
  • DISPLAY APPARATUS AND CONTROL METHOD FOR HIGH DISPLAY BANDWIDTH THEREOF
    Publication number: 20200233822
    Abstract: A display apparatus is provided. The display apparatus includes a display panel and a display controller. The display controller is electrically connected to a USB Type-C interface of a host via a USB Type-C interface of the display apparatus. In response to the USB Type-C interface of the display apparatus being in a USB Type-C default pin-assignment mode, the display controller receives an image signal from the host via two USB SuperSpeed channels of the USB Type-C interface of display apparatus. In response to a display mode of the display apparatus satisfying a specific condition, the display controller controls the USB Type-C interface of the display apparatus to enter a USB Type-C first pin assignment mode, so that the host utilizes the four USB SuperSpeed channels of the USB Type-C interface of the display apparatus to transmit the image signal to the display controller.
    Type: Application
    Filed: July 2, 2019
    Publication date: July 23, 2020
    Inventors: Li Fan ZHENG, Yong Qiang LI, Yong Bo LI, Jun Xin QIU, Wen Long YANG
  • Method and system for interactive 3D scope placement and measurements for kidney stone removal procedure
    Patent number: 10716626
    Abstract: The present teaching relates to interactive medical image processing for surgical procedure planning. In one example, a three dimensional (3D) image of a kidney is obtained. The three dimensional image is rendered on a display screen. An input is received from a user specifying a location with respect to a representation of the kidney in the rendered three dimensional image. A representation of an instrument is rendered on the display screen based on the location. The instrument is automatically aligned with an infundibulum pathway of calyx at the location with respect to the kidney. A graphical line extension is rendered on the display screen to visualize the alignment of the instrument. One or more measurements related to the kidney are determined based on the location and an anatomical structure of the kidney.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 21, 2020
    Assignee: EDDA TECHNOLOGY, INC.
    Inventors: Cheng-Chung Liang, Guo-Qing Wei, Li Fan, Xiaolan Zeng, Jianzhong Qian
  • Method and system for surgical planning in a mixed reality environment
    Patent number: 10679417
    Abstract: The present teaching relates to method and system for aligning a virtual anatomic model. The method generates a virtual model of an organ of a patient, wherein the virtual model includes at least three virtual markers. A number of virtual spheres equal to a the number of virtual markers are generated, wherein the virtual spheres are disposed on the virtual model of the organ of the patient and associated with the virtual markers. A first position of the virtual spheres and the virtual markers is recorded. The virtual spheres are placed to coincide with physical markers disposed on the patient and a second position of the virtual spheres is recorded. A transformation of the virtual spheres and the virtual markers based on the first and second positions is computed and the virtual model of the organ is aligned with the patient based on the computed transformation.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: EDDA TECHNOLOGY, INC.
    Inventors: Guo-Qing Wei, Xiaolan Zeng, Xiaonan Zang, Li Fan, Jianzhong Qian, Cheng-Chung Liang, Jiahong Dong
  • Power semiconductor device integrated with ESD protection circuit under source pad, drain pad, and/or gate pad
    Patent number: 10665709
    Abstract: A semiconductor device includes a substrate, a power device, a protection circuit, a dielectric layer, a drain pad, a source pad, and a gate pad. The power device and the protection circuit are disposed on the substrate. The power device includes a drain electrode, a source electrode, and a gate electrode. The protection circuit has a first terminal electrically connected with the source pad and a second terminal electrically connected with the gate pad. The dielectric layer is disposed on the power device and the protection circuit. The drain pad, the source pad, and the gate pad are disposed on the dielectric layer and respectively electrically connected with the drain electrode, the source electrode, and the gate electrode. At least part of the protection circuit is disposed under the source pad, the gate pad, or the drain pad.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 26, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Po-Chin Peng
  • ELIGIBILITY PREDICTIONS FOR INSTANT BOOKING IN AN ONLINE MARKETPLACE
    Publication number: 20200134513
    Abstract: Systems and methods are provided for receiving a request for services in a given location from a client device operated by a user and generating a set of features based on information included in the request for services in the given location. The systems and methods further provide for analyzing the set of features using a machine learning model to predict whether only services that can be instantly booked should be provided in response to the request for services in the given location, analyzing a prediction output by the machine learning model to determine that only services that can be instantly booked should be provided in response to the request for services in the given location, and generating a list with only services that can be instantly booked.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: Yi Hou, Li Fan, Trunal Bhanse, Andrew Chen
  • ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    Publication number: 20200098740
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 26, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Li-Fan CHEN, Chih-Hsuan LIN, Yu-Kai WANG, Hung-Wei CHEN, Ching-Wen WANG, Ting-You LIN, Chun-Chih CHEN
  • Container-type combination house and construction method thereof
    Patent number: 10584503
    Abstract: Disclosed is a container type combined house, which is mainly composited by connecting a foam cement composite bottom board, foam cement composite wall boards, a foam cement composite top board, specially-shaped bottom beams, a specially-shaped top beam and a specially-shaped column. The specially-shaped bottom beams, the specially-shaped top beam and the specially-shaped column are matched in shape with steel boundary ribs of the foam cement composite bottom board, the foam cement composite wall boards and the foam cement composite top board, and are connected and fixed in a mechanical or welding manner. According to the construction method of the container type combined house, the combined house is easily assembled, with good comprehensive performance.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: March 10, 2020
    Assignee: TAIKONG INTELLIGENT CONSTRUCTION CO., LTD.
    Inventor: Li Fan
  • Distal tip two piece external expansion anchor
    Patent number: 10582920
    Abstract: Examples of a suture anchor (100) having a non-expandable body (105) and expendable cap (110) are described herein. In response to an axial insertion force that brings the non-expandable body and expendable cap together inside a bone hole, the expendable cap expands radially. This creates a radial force of expansion that advantageously augments an interference fit between the suture anchor and bone hole, which leads to higher fixation strength. Other examples include retention features that inhibit the expendable cap from returning back into its unexpanded state. This advantageously maintains the radial force of expansion against the surrounding pressure of the walls of the bone hole pressing back on the suture.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 10, 2020
    Assignee: Smith & Nephew, Inc.
    Inventors: Richard M. Lunn, Timothy Young, Matthew Edwin Koski, John Slusarz, Paul R. Duhamel, Wei Li Fan, Steven Astorino
  • Etching to Reduce Line Wiggling
    Publication number: 20200075405
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • SEMICONDUCTOR LAYER STRUCTURE WITH A THICK BUFFER LAYER
    Publication number: 20200067280
    Abstract: A semiconductor layer structure may include a substrate, a buffer layer formed on the substrate, and a set of epitaxial layers formed on the buffer layer. The buffer layer may have a thickness that is greater than 2 micrometers (?m). The set of epitaxial layers may include a quantum well layer. A quantum well intermixing region may be formed in association with the quantum well layer and a material diffused from a region of a surface of the semiconductor layer structure.
    Type: Application
    Filed: May 28, 2019
    Publication date: February 27, 2020
    Inventor: Li FAN
  • Heterojunction semiconductor device for reducing parasitic capacitance
    Patent number: 10573736
    Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: February 25, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang, Wen-Chia Liao, Ching-Chuan Shiue, Shih-Peng Chen
  • METHOD AND SYSTEM FOR CONSISTENT, REPEATABLE, AND SAFE CRYOSPRAY TREATMENT OF AIRWAY TISSUE
    Publication number: 20200054380
    Abstract: A method and system for automated and semi-automated predictable, consistent, safe, effective, and lumen-specific and patient-specific cryospray treatment of airway tissue in which treatment duration is automatically set by the system following entry of patient information and treatment location information into the system by the user, and treatment spray is automatically stopped by the system when the automatically selected treatment duration has been achieved as determined by the system.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Wendelin Maners, Ellen Sheets, Rafael Cordero, Marc Davidson, Wei Li Fan, David Sherrill, Brian M. Hanley, Amy Sarli, Stephen Griffin, Heather V. Hawkes
  • Heterojunction Semiconductor Device for Reducing Parasitic Capacitance
    Publication number: 20200020791
    Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Li-Fan LIN, Chun-Chieh YANG, Wen-Chia LIAO, Ching-Chuan SHIUE, Shih-Peng CHEN
  • Multiple patterning method using mask portions to etch semiconductor substrate
    Patent number: 10535532
    Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
  • SEMICONDUCTOR DEVICE
    Publication number: 20190386128
    Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.
    Type: Application
    Filed: August 26, 2019
    Publication date: December 19, 2019
    Inventors: Li-Fan LIN, Chun-Chieh YANG, Ying-Chen LIU
  • Method and system for estimating a deflated lung shape for video assisted thoracic surgery in augmented and mixed reality
    Patent number: 10499992
    Abstract: The present teaching relates to surgical procedure assistance. In one example, a first volume of air inside a lung is obtained based on a first image of the lung captured prior to a surgical procedure. The lung has a first shape on the first image. A second volume of air deflated from the lung is determined based on a second image of the lung captured during the surgical procedure. A second shape of the lung is estimated based on the first shape of the lung and the first air volume inside the lung and second volume of air deflated from the lung. A surgical plan is updated based on the estimated second shape of the lung.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 10, 2019
    Assignee: EDDA TECHNOLOGY, INC.
    Inventors: Guo-Qing Wei, Li Fan, Cheng-Chung Liang, Jianzhong Qian, Xiaolan Zeng
  • Method and system for consistent, repeatable, and safe cryospray treatment of airway tissue
    Patent number: 10492843
    Abstract: A method and system for automated and semi-automated predictable, consistent, safe, effective, and lumen-specific and patient-specific cryospray treatment of airway tissue in which treatment duration is automatically set by the system following entry of patient information and treatment location information into the system by the user, and treatment spray is automatically stopped by the system when the automatically selected treatment duration has been achieved as determined by the system.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: December 3, 2019
    Assignee: CSA Medical, Inc.
    Inventors: Wendelin Maners, Ellen Sheets, Mark Davidson, Rafael Cordero, Wei Li Fan, David Seemes Sherrill, Brian M. Hanley, Amy Sarli, Heather Hawkes, Stephen Griffin
  • Bias circuit and power amplifier circuit
    Patent number: 10498291
    Abstract: A bias circuit and a power amplifier circuit are provided in the present disclosure. The bias circuit includes an output node, a power detecting circuit, a first constant voltage bias circuit, and a constant current bias circuit. The output node is configured to provide a bias signal to a power amplifier unit. The output node is further configured to receive an input signal of the power amplifier unit. The power detecting circuit is configured to detect a power of the input signal of the power amplifier unit to provide a first control signal. The first constant voltage bias circuit is configured to selectively provide a first signal to the output node according to the first control signal. The constant current bias circuit provides a second signal to the output node.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: December 3, 2019
    Assignee: AIROHA TECHNOLOGY CORP.
    Inventor: Li-Fan Tsai