Patents by Inventor Li-Han Chen

Li-Han Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10550243
    Abstract: A superabsorbent polymer includes polymeric particles, surface cross-linking agents and an extract of a plant of Sapindaceae. The polymeric particles have cross-linking inside the polymeric particles. The surface cross-linking agents are covalently bound to the surface of the polymeric particles so as to constitute a layer of surface cross-linked region at the surface of each polymeric particle, and the extract of the plant of Sapindaceae covers the surface of the polymeric particles.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: February 4, 2020
    Assignee: Formosa Plastics Corporation
    Inventors: Zhong-Yi Chen, Yu-Yen Chuang, Li-Han Huang, Yu-Sam Lin, Feng-Yi Chen, Ching-Hua Liang
  • Patent number: 10510654
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 10510664
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 10504751
    Abstract: Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Cheng-Hsien Hsieh, Li-Han Hsu, Lai Wei Chih
  • Publication number: 20190371261
    Abstract: The disclosure provides a storage medium, an expansion base and an operation method thereof combined with a portable electronic device. The portable electronic device is pre-installed with an application program and includes a touch screen. The expansion base is paired with the portable electronic device and accommodates the portable electronic device. When the portable electronic device is accommodated inside the expansion base, a touch window on the surface of the expansion base exposes at least a portion of the touch screen, and the portable electronic device executes the application program to automatically adjust a size or a display position of a display image of the touch screen to correspond to the touch window.
    Type: Application
    Filed: May 13, 2019
    Publication date: December 5, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Che-Wei Liang, Xiu-Yu Lin, Yi-Han Liao, Sheng-Chieh Tang, Chieh-Yu Chan, Chiao-Tsu Chiang, Wen-Yi Chiu, Wei-Chih Hsu, Li-Fang Chen, Yi-Jing Lin
  • Patent number: 10497607
    Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 3, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Li-Han Chen, Chun-Chieh Chiu, Wei-Chuan Tsai, Yen-Tsai Yi
  • Patent number: 10497617
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Patent number: 10475768
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10459431
    Abstract: A three-dimensional printing apparatus includes a liquid tank, a curing platform and a light source device. A bearing member of the liquid tank is air proof, and forms an accommodating space with a side wall of the liquid tank. The curing platform is disposed at a first side of the bearing member corresponding to the accommodating space for allowing a workpiece to be cured on a surface thereof. After the accommodating space accommodates a liquid material, a curing light beam provided by a light source device disposed at a second side of the bearing member opposite to the accommodating space cures at least part of the liquid material on a surface of the curing platform via the bearing member. The use of a solid release material between the curing platform and the bearing member may be omitted. Methods for printing and releasing a three-dimensional workpiece are also provided.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 29, 2019
    Assignee: YOUNG OPTICS INC.
    Inventors: Li-Han Wu, Yea-Ru Sheu, Ming-Feng Ho, Chao-Shun Chen
  • Publication number: 20190295955
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190197235
    Abstract: A setting method for a server adapted for setting the server to run a virtual machine is provided. The setting method includes: obtaining a first memory address when a first service function of the virtual machine is called in a startup procedure of the virtual machine; correcting a memory block corresponding to the first memory address, to have an operation of the virtual being interrupted when the memory block is called by the virtual machine; determining, by a management module of the virtual machine, whether a script called by the first service function is executable or not, when the operation of the virtual machine is interrupted; if the script is not executable, interrupting, by the management module, the script called by the first service function; and if the script is executable, allowing, by the management module, the first service function to execute the script.
    Type: Application
    Filed: October 2, 2018
    Publication date: June 27, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tzi-Cker CHIUEH, Li-Han CHEN, Yu-Hsuan WANG, Chuan-Yu CHO, Yi-Ting CHAO
  • Patent number: 10319681
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10310327
    Abstract: A backlight module includes a supporting plate, a light source module, and an optical modulation film. The light source module includes a plurality of light sources disposed on a supporting surface of the supporting plate. The optical modulation film is disposed above the light source module and has a plurality of light emitting holes. Light from the light source module is distributed by the optical modulation film and emitted via light emitting holes at different positions. The optical modulation film has a periphery area and a central area. An average perpendicular distance between the periphery area and the supporting surface is different from an average perpendicular distance between the central area and the supporting surface.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 4, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yung-Hsin Liu, Chiung-Han Wang, Li-Jia Chen
  • Patent number: 10290584
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190122925
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Publication number: 20190057895
    Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.
    Type: Application
    Filed: September 21, 2017
    Publication date: February 21, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Li-Han Chen, Chun-Chieh Chiu, Wei-Chuan Tsai, Yen-Tsai Yi
  • Patent number: 10199269
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Publication number: 20180366368
    Abstract: The present invention provides a method for forming a contact structure, the method includes proving a substrate. An oxygen-containing dielectric layer is formed on the substrate. Next, a non-oxygen layer is formed on the oxygen-containing dielectric layer and a contact hole is then formed in the oxygen-containing dielectric layer. A metal layer is then formed in the contact hole and on the non-oxygen layer, with the non-oxygen layer disposed between the oxygen-containing dielectric layer and the metal layer. An anneal process is then performed to the metal layer, and a conductive layer is filled in the contact hole.
    Type: Application
    Filed: June 18, 2017
    Publication date: December 20, 2018
    Inventors: Chun-Chieh Chiu, Wei-Chuan Tsai, Yen-Tsai Yi, Li-Han Chen
  • Patent number: 10068797
    Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Shu Min Huang, Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Publication number: 20180151428
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang