Patents by Inventor Li-Han Hsu

Li-Han Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages
    Patent number: 9786567
    Abstract: An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Li-Han Hsu, Sao-Ling Chiu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Lin
  • Dummy structure for chip-on-wafer-on-substrate
    Patent number: 9754831
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
    Publication number: 20170250138
    Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.
    Type: Application
    Filed: June 1, 2016
    Publication date: August 31, 2017
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
  • Redistribution layers in semiconductor packages and methods of forming same
    Patent number: 9741690
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Opening in the Pad for Bonding Integrated Passive Device in InFO Package
    Publication number: 20170188458
    Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
  • Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages
    Publication number: 20170133282
    Abstract: An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.
    Type: Application
    Filed: January 25, 2017
    Publication date: May 11, 2017
    Inventors: Wei-Cheng Wu, Li-Han Hsu, Sao-Ling Chiu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Lin
  • Dummy Metal with Zigzagged Edges
    Publication number: 20170084529
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 23, 2017
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages
    Patent number: 9581638
    Abstract: An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Li-Han Hsu, Sao-Ling Chiu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Lin
  • Dummy Structure for Chip-on-Wafer-on-Substrate
    Publication number: 20160358818
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Fruit bowl
    Patent number: D777525
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 31, 2017
    Assignee: Seville Classics Inc.
    Inventor: Li-Han Hsu
  • Napkin holder
    Patent number: D778119
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 7, 2017
    Assignee: Seville Classics Inc
    Inventors: Li-Han Hsu, Cynthia J. Luff
  • Mesh basket
    Patent number: D779206
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: February 21, 2017
    Assignee: Seville Classics, Inc.
    Inventors: Li-Han Hsu, Cynthia J. Luff
  • Organizer
    Patent number: D781055
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: March 14, 2017
    Assignee: Seville Classics, Inc
    Inventors: Li-Han Hsu, Cynthia J. Luff
  • Drawer organizer
    Patent number: D786629
    Type: Grant
    Filed: April 10, 2016
    Date of Patent: May 16, 2017
    Assignee: Seville Classics, Inc
    Inventor: Li-Han Hsu
  • Shoe rack
    Patent number: D787242
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 23, 2017
    Assignee: Seville Classics, Inc.
    Inventor: Li-Han Hsu
  • Drawer organizer
    Patent number: D787278
    Type: Grant
    Filed: April 10, 2016
    Date of Patent: May 23, 2017
    Assignee: Seville Classics Inc.
    Inventor: Li-Han Hsu
  • Drawer organizer
    Patent number: D787279
    Type: Grant
    Filed: April 10, 2016
    Date of Patent: May 23, 2017
    Assignee: Seville Classics Inc
    Inventor: Li-Han Hsu
  • Mesh basket
    Patent number: D792099
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: July 18, 2017
    Assignee: Seville Classics, Inc.
    Inventors: Li-Han Hsu, Cynthia J. Luff
  • Drawer organizer
    Patent number: D795655
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: August 29, 2017
    Assignee: Seville Classics Inc.
    Inventor: Li-Han Hsu
  • Mesh holder
    Patent number: D799831
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 17, 2017
    Assignee: Seville Classics Inc
    Inventors: Li-Han Hsu, Cynthia J. Luff