Patents by Inventor Li-Qun Xia

Li-Qun Xia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090137132
    Abstract: Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.
    Type: Application
    Filed: February 4, 2009
    Publication date: May 28, 2009
    Inventors: Ritwik Bhatia, Li-Qun Xia, Chad Peterson, Hichem M'Saad
  • Publication number: 20090107626
    Abstract: Embodiments described herein provide a method of processing a substrate. The method includes depositing an interface adhesion layer between a conductive material and a dielectric material such that the interface adhesion layer provides increased adhesion between the conductive material and the dielectric material. In one embodiment a method for processing a substrate is provided. The method comprises depositing an interface adhesion layer on a substrate comprising a conductive material, exposing the interface adhesion layer to a nitrogen containing plasma, and depositing a dielectric layer on the interface adhesion layer after exposing the interface adhesion layer to the nitrogen containing plasma.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 30, 2009
    Inventors: Yong-Won Lee, Sang M. Lee, Meiyee(Maggie Le) Shek, Weifeng Ye, Li-Qun Xia, Derek R. Witty, Thomas Nowak, Juan Carlos Rocha-Alvarez, Jigang Li
  • Publication number: 20090104764
    Abstract: A method for forming a structure includes forming at least one feature across a surface of a substrate. A nitrogen-containing dielectric layer is formed over the at least one feature. A first portion of the nitrogen-containing layer on at least one sidewall of the at least one feature is removed at a first rate and a second portion of the nitrogen-containing layer over the substrate adjacent to a bottom region of the at least one feature is removed at a second rate. The first rate is greater than the second rate. A dielectric layer is formed over the nitrogen-containing dielectric layer.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 23, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Mihaela Balseanu, Victor Nguyen, Derek R. Witty, Hichem M'Saad, Haichun Yang, Xinliang Lu, Chien-Teh Kao, Mei Chang
  • Publication number: 20090093100
    Abstract: The present invention generally provides a method for forming multilevel interconnect structures, including multilevel interconnect structures that include an air gap. One embodiment provides a method for forming conductive lines in a semiconductor structure comprising forming trenches in a first dielectric layer, wherein air gaps are to be formed in the first dielectric layer, depositing a conformal dielectric barrier film in the trenches, wherein the conformal dielectric barrier film comprises a low k dielectric material configured to serve as a barrier against a wet etching chemistry used in forming the air gaps in the first dielectric layer, depositing a metallic diffusion barrier film over the conformal low k dielectric layer, and depositing a conductive material to fill the trenches.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventors: Li-Qun Xia, Huiwen Xu, Mihaela Balseanu, Meiyee (Maggie Le) Shek, Derek R. Witty, Hichem M'Saad
  • Publication number: 20090093112
    Abstract: A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventors: AMIR AL-BAYATI, Alexandros T. Demos, Kang Sub Yim, Mehul Naik, Zhenjiang 'David' Cui, Mihaela Balseanu, Meiyee (Maggie Le) Shek, Li-Qun Xia
  • Publication number: 20090093132
    Abstract: The present invention generally provides a method for forming a dielectric barrier with lowered dielectric constant, improved etching resistivity and good barrier property. One embodiment provides a method for processing a semiconductor substrate comprising flowing a precursor to a processing chamber, wherein the precursor comprises silicon-carbon bonds and carbon-carbon bonds, and generating a low density plasma of the precursor in the processing chamber to form a dielectric barrier film having carbon-carbon bonds on the semiconductor substrate, wherein the at least a portion of carbon-carbon bonds in the precursor is preserved in the low density plasma and incorporated in the dielectric barrier film.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventors: HUIWEN XU, Yijun Liu, Li-Qun Xia, Derek R. Witty, Hichem M'Saad
  • Publication number: 20090087977
    Abstract: The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 2, 2009
    Inventors: MATTHEW SPULLER, Melody Agustin, Meiyee (Maggie Le) Shek, Li-Qun Xia, Reza Arghavani
  • Patent number: 7501355
    Abstract: Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: March 10, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Ritwik Bhatia, Li-Qun Xia, Chad Peterson, Hichem M'Saad
  • Publication number: 20090053902
    Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.
    Type: Application
    Filed: October 21, 2008
    Publication date: February 26, 2009
    Inventors: Kang Sub Yim, Melissa M. Tam, Dian Sugiarto, Chi-I Lang, Peter Wai-Man Lee, Li-Qun Xia
  • Publication number: 20090017640
    Abstract: Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of the resulting boron-containing film. The boron-containing films have a stress between about ?10 GPa and 10 GPa and may be used as boron source layers or as strain-inducing layers.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 15, 2009
    Inventors: Jeong-Uk Huh, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty, Hichem M'Saad
  • Publication number: 20090011148
    Abstract: Adhesion between a copper metallization layer and a dielectric barrier film may be promoted by stabilizing a flow of a silicon-containing precursor in a divert line leading to the chamber exhaust. The stabilized gas flow is then introduced to the processing chamber to precisely form a silicide layer over the copper. This silicidation step creates a network of strong Cu—Si bonds that prevent delamination of the barrier layer, while not substantially altering the sheet resistance and other electrical properties of the resulting metallization structure.
    Type: Application
    Filed: June 17, 2008
    Publication date: January 8, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Bok Heon Kim, Lester A. D'Cruz, Zhenjiang Cui, Girish A. Dixit, Visweswaren Sivaramakrishnan, Hichem M'Saad, Meiyee Shek, Li-Qun Xia
  • Patent number: 7465659
    Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: December 16, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Melissa M. Tam, Dian Sugiarto, Chi-I Lang, Peter Wai-Man Lee, Li-Qun Xia
  • Patent number: 7459404
    Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including introducing an organosilicon compound and an oxidizing gas at a first ratio of organosilicon compound to oxidizing gas into the processing chamber, generating a plasma of the oxidizing gas and the organosilicon compound to form an initiation layer on a barrier layer comprising at least silicon and carbon, introducing the organosilicon compound and the oxidizing gas at a second ratio of organosilicon compound to oxidizing gas greater than the first ratio into the processing chamber, and depositing a first dielectric layer adjacent the dielectric initiation layer.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: December 2, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Lihua Li, Tzu-Fang Huang, Jerry Sugiarto, legal representative, Li-Qun Xia, Peter Wai-Man Lee, Hichem M'Saad, Zhenjiang Cui, Sohyun Park, Dian Sugiarto
  • Publication number: 20080292798
    Abstract: Methods for forming boron-containing films are provided. The methods include introducing a boron-containing precursor and a nitrogen or oxygen-containing precursor into a chamber and forming a boron nitride or boron oxide film on a substrate in the chamber. In one aspect, the method includes depositing a boron-containing film and then exposing the boron-containing film to the nitrogen-containing or oxygen-containing precursor to incorporate nitrogen or oxygen into the film. The deposition of the boron-containing film and exposure of the film to the precursor may be performed for multiple cycles to obtain a desired thickness of the film. In another aspect, the method includes reacting the boron-containing precursor and the nitrogen-containing or oxygen-containing precursor to chemically vapor deposit the boron nitride or boron oxide film.
    Type: Application
    Filed: June 19, 2007
    Publication date: November 27, 2008
    Inventors: Jeong-Uk Huh, Mihaela Balseanu, Li-Qun Xia, Victor T. Nguyen, Derek R. Witty, Hichem M'saad
  • Patent number: 7435685
    Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: October 14, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Gerardo A. Delgadino, Yan Ye, Neungho Shin, Yunsang Kim, Li-Qun Xia, Tzu-Fang Huang, Lihua Li Huang, Joey Chiu, Xiaoye Zhao, Fang Tian, Wen Zhu, Ellie Yieh
  • Patent number: 7422774
    Abstract: The present invention generally provides a method for depositing a low dielectric constant film using an e-beam treatment. In one aspect, the method includes delivering a gas mixture comprising one or more organosilicon compounds and one or more hydrocarbon compounds having at least one cyclic group to a substrate surface at deposition conditions sufficient to deposit a non-cured film comprising the at least one cyclic group on the substrate surface. The method further includes substantially removing the at least one cyclic group from the non-cured film using an electron beam at curing conditions sufficient to provide a dielectric constant less than 2.5 and a hardness greater than 0.5 GPa.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: September 9, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Yi Zheng, Srinivas D. Nemani, Li-Qun Xia, Eric Hollar, Kang Sub Yim
  • Patent number: 7422776
    Abstract: Low K dielectric films exhibiting low mechanical stress may be formed utilizing various techniques in accordance with the present invention. In one embodiment, carbon-containing silicon oxide films are formed by plasma-assisted chemical vapor deposition at low temperatures (300° C. or less). In accordance with another embodiment, as-deposited carbon containing silicon oxide films incorporate a porogen whose subsequent liberation reduces film stress.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: September 9, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Lihua Li Huang, Francimar Schmitt, Li-Qun Xia
  • Publication number: 20080213997
    Abstract: A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer.
    Type: Application
    Filed: December 5, 2007
    Publication date: September 4, 2008
    Applicant: Applied Materials, Inc.
    Inventors: Sang M. Lee, Vladimir Zubkov, Zhenijiang Cui, Meiyee Shek, Li-Qun Xia, Hichem M'Saad
  • Publication number: 20080182404
    Abstract: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 31, 2008
    Inventors: ALEXANDROS T. DEMOS, Li-Qun Xia, Bok Hoen Kim, Derek R. Witty, Hichem M'Saad
  • Publication number: 20080145998
    Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
    Type: Application
    Filed: September 13, 2006
    Publication date: June 19, 2008
    Applicant: APPLIED MATERIALS, INC.
    Inventors: GERARDO A. DELGADINO, Yan Ye, Neungho Shin, Yunsang Kim, Li-Qun Xia, Tzu-Fang Huang, Lihua Li Huang, Joey Chiu, Xiaoye Zhao, Fang Tian, Wen Zhu, Ellie Yieh