Abstract: The present invention relates to a method of reducing the level of uric acid in a subject, which comprises administering to said subject an effective amount of a fermentation product of Tenacibaculum sp. Also provided are a method of preventing and/or treating a disease or disorder related to hyperuricemia, a method of increasing the digestion of uric acid and a method of producing uricase.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region.

Abstract: Methods for an oxide layer over an epitaxial layer. In an embodiment, a method includes forming an epitaxial layer of semiconductor material over a semiconductor substrate; forming an oxide layer over the epitaxial layer; applying a solution including an oxidizer to the oxide layer; and cleaning the oxide layer with a cleaning solution. In another embodiment, a densification process is applied to an oxide layer including treating with thermal energy, UV energy, or both. In an embodiment for a gate-all-around device, the cleaning process is applied to an oxide layer over an epitaxial portion of a fin. Additional methods are disclosed.

Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.

Abstract: A method of forming an ultra-shallow junction in a semiconductor substrate. The method includes forming an amorphous region in a semiconductor substrate by performing a pre-amorphization implant step and implanting one or more dopants in the amorphous region by performing a monolayer doping step. The semiconductor substrate is then thermally treated to activate the implanted dopant in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The thermal treatment can be performed without any oxide cap overlying the implanted amorphous region.

Abstract: The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.

Abstract: An electronic apparatus is disclosed, which comprises: a housing, configured with a plurality of inlets and one outlet; a plurality of electronic elements, disposed inside the housing; and a plurality of gates, arranged at positions corresponding to the plural inlets in an one-by-one manner; wherein, the plural electronic elements are activated while the electronic apparatus is enabled for causing the temperature of the plural electronic elements to be raised to their respective working temperatures, thereby, causing a plurality of heating zones to be formed inside the housing at positions respectively corresponding to the plural inlets; and by enabling each gate to be configured with one thermal expansion element that is enabled to deform with the temperature variation of the corresponding heating zone, each gate is enabled to move between a first position and a second position according to the deformation of the corresponding thermal expansion element.

Abstract: The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.

Abstract: A heat dissipation device includes a fan module, a first plate structure and a fin assembly. The fan module includes a fan outlet. The first plate structure is disposed at the fan outlet. The thermal conductance of the first plate structure is above 100 W/(m·K). The first plate structure includes a heat-absorbing and a heat-dissipation surface. The heat-absorbing surface includes a heat-absorbing region in thermal contact with a heat source. The heat-dissipation surface includes a heat-dissipation region. The fin assembly is disposed on the heat-dissipation surface and in thermal contact with the heat-dissipation surface. The fan module is adapted to exhaust an air flow flowing above the heat-dissipation surface via the fan outlet. The air flow flows through the heat-dissipation region before through the fin assembly. The distance between the fan outlet and the heat-dissipation region is greater than the distance between the fan outlet and the fin assembly.

Abstract: The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.

Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a first portion configured to hold an overlying wafer. The first portion includes a central region and an edge region circumscribing the central region. The first portion further including an upper surface and a lower surface. The apparatus further includes a second portion extending beyond an outer radius of the wafer. The second portion including an upper surface and a lower surface. The lower surface of the first portion in the central region has a first reflective characteristic. The lower surface of the first portion in the edge region and the second portion have a second reflective characteristic.

Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness.

Abstract: An electronic apparatus with improved heat dissipation comprises a first body with a first shell and a second shell, a second body, a coupling device and a linkage device. The first shell is pivotally connected to the second shell to form an accommodation space. The first shell can pivot relative to the second shell to enlarge the accommodation space and form an opening between the first shell and the second shell. The coupling device couples the second body and the second shell to pivot the second body relative to the second shell to expose or hide the first shell. The linkage device drives the first shell to pivot relative to the second shell. When the second body pivots relative to the second shell toward a first direction, the linkage device drives the first shell to pivot relative to the second shell toward a second direction opposite to the first direction.

Abstract: An electronic apparatus is disclosed, which comprises: a housing, configured with a plurality of inlets and one outlet; a plurality of electronic elements, disposed inside the housing; and a plurality of gates, arranged at positions corresponding to the plural inlets in an one-by-one manner; wherein, the plural electronic elements are activated while the electronic apparatus is enabled for causing the temperature of the plural electronic elements to be raised to their respective working temperatures, thereby, causing a plurality of heating zones to be formed inside the housing at positions respectively corresponding to the plural inlets; and by enabling each gate to be configured with one thermal expansion element that is enabled to deform with the temperature variation of the corresponding heating zone, each gate is enabled to move between a first position and a second position according to the deformation of the corresponding thermal expansion element.

Abstract: A heat dissipation module, comprising: a fan; and a heat dissipating fin; a heat conducting element, made of a conductive material, and composed of a first conductive component and two second conductive components in a manner that the first conductive component is disposed engaging with a heating element while allowing the two second conductive components to engage with the heat dissipating fin; and a wall element; wherein, the heat from the heating element is conducted to the first conductive component where it is further being dividedly conducted to the two second conductive components; and the air flow blowing from the fan is guided to the heating element and then it is blocked by the wall element for diverting the air flow toward the heat dissipating fin from an air intake side to an air outlet side, and then to be discharged out of the heat dissipating module through an outlet.

Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.

Abstract: A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.

Abstract: An electronic apparatus and a keyboard supporting module thereof are provided. The electronic apparatus includes a heat source, the keyboard supporting module and a push-button key module. The keyboard supporting module includes a keyboard supporting structure and an insulator. The keyboard supporting structure is thermally connected to the heat source. Particularly, the keyboard supporting structure supports the push-button key module with the insulator.

Abstract: An electronic apparatus with improved heat dissipation comprises a first body with a first shell and a second shell, a second body, a coupling device and a linkage device. The first shell is pivotally connected to the second shell to form an accommodation space. The first shell can pivot relative to the second shell to enlarge the accommodation space and form an opening between the first shell and the second shell. The coupling device couples the second body and the second shell to pivot the second body relative to the second shell to expose or hide the first shell. The linkage device drives the first shell to pivot relative to the second shell. When the second body pivots relative to the second shell toward a first direction, the linkage device drives the first shell to pivot relative to the second shell toward a second direction opposite to the first direction.

Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.